Sagar Shrikant Kadam d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's ... PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>		2020-08-04 09:19:41 +08:00
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cache.h	riscv: sifive: fu540: enable all cache ways from U-Boot proper	2020-07-03 15:09:06 +08:00
clk.h	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
gpio.h	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
reset.h	sifive: reset: add DM based reset driver for SiFive SoC's	2020-08-04 09:19:41 +08:00
spl.h	riscv: sifive: fu540: add SPL configuration	2020-06-04 09:44:09 +08:00