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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
410 lines
11 KiB
C
410 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
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* Copyright (C) 2000-2010 Broadcom Corporation
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* Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#define HSSPI_PP 0
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#define SPI_MAX_SYNC_CLOCK 30000000
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/* SPI Control register */
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#define SPI_CTL_REG 0x000
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#define SPI_CTL_CS_POL_SHIFT 0
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#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
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#define SPI_CTL_CLK_GATE_SHIFT 16
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#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
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#define SPI_CTL_CLK_POL_SHIFT 17
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#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
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/* SPI Interrupts registers */
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#define SPI_IR_STAT_REG 0x008
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#define SPI_IR_ST_MASK_REG 0x00c
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#define SPI_IR_MASK_REG 0x010
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#define SPI_IR_CLEAR_ALL 0xff001f1f
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/* SPI Ping-Pong Command registers */
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#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
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#define SPI_CMD_OP_SHIFT 0
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#define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
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#define SPI_CMD_PFL_SHIFT 8
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#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
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#define SPI_CMD_SLAVE_SHIFT 12
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#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
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/* SPI Ping-Pong Status registers */
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#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
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#define SPI_STAT_SRCBUSY_SHIFT 1
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#define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
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/* SPI Profile Clock registers */
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#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
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#define SPI_PFL_CLK_FREQ_SHIFT 0
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#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
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#define SPI_PFL_CLK_RSTLOOP_SHIFT 15
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#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
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/* SPI Profile Signal registers */
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#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
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#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
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#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
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#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
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#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
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#define SPI_PFL_SIG_ASYNCIN_SHIFT 16
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#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
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/* SPI Profile Mode registers */
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#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
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#define SPI_PFL_MODE_FILL_SHIFT 0
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#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
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#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
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#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
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#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
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#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
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#define SPI_PFL_MODE_3WIRE_SHIFT 20
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#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
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/* SPI Ping-Pong FIFO registers */
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#define HSSPI_FIFO_SIZE 0x200
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#define HSSPI_FIFO_BASE (0x200 + \
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(HSSPI_FIFO_SIZE * HSSPI_PP))
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/* SPI Ping-Pong FIFO OP register */
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#define HSSPI_FIFO_OP_SIZE 0x2
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#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
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#define HSSPI_FIFO_OP_BYTES_SHIFT 0
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#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
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#define HSSPI_FIFO_OP_MBIT_SHIFT 11
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#define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
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#define HSSPI_FIFO_OP_CODE_SHIFT 13
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#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
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#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
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#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
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struct bcm63xx_hsspi_priv {
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void __iomem *regs;
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ulong clk_rate;
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uint8_t num_cs;
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uint8_t cs_pols;
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uint speed;
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};
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static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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if (cs >= priv->num_cs) {
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printf("no cs %u\n", cs);
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return -EINVAL;
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}
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return 0;
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}
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static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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/* clock polarity */
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if (mode & SPI_CPOL)
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setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
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else
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clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
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return 0;
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}
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static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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priv->speed = speed;
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return 0;
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}
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static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
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struct dm_spi_slave_platdata *plat)
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{
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uint32_t clr, set;
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/* profile clock */
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set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
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set = DIV_ROUND_UP(2048, set);
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set &= SPI_PFL_CLK_FREQ_MASK;
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set |= SPI_PFL_CLK_RSTLOOP_MASK;
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writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
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/* profile signal */
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set = 0;
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clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
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SPI_PFL_SIG_LATCHRIS_MASK |
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SPI_PFL_SIG_ASYNCIN_MASK;
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/* latch/launch config */
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if (plat->mode & SPI_CPHA)
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set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
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else
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set |= SPI_PFL_SIG_LATCHRIS_MASK;
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/* async clk */
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if (priv->speed > SPI_MAX_SYNC_CLOCK)
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set |= SPI_PFL_SIG_ASYNCIN_MASK;
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clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
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/* global control */
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set = 0;
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clr = 0;
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/* invert cs polarity */
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if (priv->cs_pols & BIT(plat->cs))
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clr |= BIT(plat->cs);
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else
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set |= BIT(plat->cs);
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/* invert dummy cs polarity */
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if (priv->cs_pols & BIT(!plat->cs))
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clr |= BIT(!plat->cs);
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else
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set |= BIT(!plat->cs);
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clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
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}
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static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
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{
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/* restore cs polarities */
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clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
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priv->cs_pols);
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}
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/*
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* BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
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* because they are controlled by HW.
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* However, it provides a mechanism to prepend write transfers prior to read
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* transfers (with a maximum prepend of 15 bytes), which is usually enough for
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* SPI-connected flashes since reading requires prepending a write transfer of
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* 5 bytes. On the other hand it also provides a way to invert each CS
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* polarity, not only between transfers like the older BCM63xx SPI driver, but
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* also the rest of the time.
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*
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* Instead of using the prepend mechanism, this implementation inverts the
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* polarity of both the desired CS and another dummy CS when the bus is
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* claimed. This way, the dummy CS is restored to its inactive value when
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* transfers are issued and the desired CS is preserved in its active value
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* all the time. This hack is also used in the upstream linux driver and
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* allows keeping CS active between trasnfers even if the HW doesn't give
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* this possibility.
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*/
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static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
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struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
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size_t data_bytes = bitlen / 8;
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size_t step_size = HSSPI_FIFO_SIZE;
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uint16_t opcode = 0;
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uint32_t val;
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const uint8_t *tx = dout;
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uint8_t *rx = din;
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if (flags & SPI_XFER_BEGIN)
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bcm63xx_hsspi_activate_cs(priv, plat);
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/* fifo operation */
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if (tx && rx)
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opcode = HSSPI_FIFO_OP_READ_WRITE;
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else if (rx)
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opcode = HSSPI_FIFO_OP_CODE_R;
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else if (tx)
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opcode = HSSPI_FIFO_OP_CODE_W;
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if (opcode != HSSPI_FIFO_OP_CODE_R)
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step_size -= HSSPI_FIFO_OP_SIZE;
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/* dual mode */
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if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
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(opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
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opcode |= HSSPI_FIFO_OP_MBIT_MASK;
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/* profile mode */
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val = SPI_PFL_MODE_FILL_MASK |
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SPI_PFL_MODE_MDRDSZ_MASK |
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SPI_PFL_MODE_MDWRSZ_MASK;
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if (plat->mode & SPI_3WIRE)
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val |= SPI_PFL_MODE_3WIRE_MASK;
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writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
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/* transfer loop */
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while (data_bytes > 0) {
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size_t curr_step = min(step_size, data_bytes);
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int ret;
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/* copy tx data */
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if (tx) {
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memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
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HSSPI_FIFO_OP_SIZE, tx, curr_step);
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tx += curr_step;
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}
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/* set fifo operation */
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writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
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priv->regs + HSSPI_FIFO_OP_REG);
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/* issue the transfer */
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val = SPI_CMD_OP_START;
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val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
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SPI_CMD_PFL_MASK;
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val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
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SPI_CMD_SLAVE_MASK;
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writel(val, priv->regs + SPI_CMD_REG);
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/* wait for completion */
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ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
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SPI_STAT_SRCBUSY_MASK, false,
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1000, false);
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if (ret) {
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printf("interrupt timeout\n");
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return ret;
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}
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/* copy rx data */
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if (rx) {
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memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
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curr_step);
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rx += curr_step;
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}
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data_bytes -= curr_step;
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}
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if (flags & SPI_XFER_END)
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bcm63xx_hsspi_deactivate_cs(priv);
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return 0;
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}
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static const struct dm_spi_ops bcm63xx_hsspi_ops = {
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.cs_info = bcm63xx_hsspi_cs_info,
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.set_mode = bcm63xx_hsspi_set_mode,
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.set_speed = bcm63xx_hsspi_set_speed,
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.xfer = bcm63xx_hsspi_xfer,
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};
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static const struct udevice_id bcm63xx_hsspi_ids[] = {
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{ .compatible = "brcm,bcm6328-hsspi", },
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{ /* sentinel */ }
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};
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static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
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struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
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/* check cs */
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if (plat->cs >= priv->num_cs) {
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printf("no cs %u\n", plat->cs);
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return -ENODEV;
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}
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/* cs polarity */
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if (plat->mode & SPI_CS_HIGH)
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priv->cs_pols |= BIT(plat->cs);
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else
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priv->cs_pols &= ~BIT(plat->cs);
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return 0;
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}
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static int bcm63xx_hsspi_probe(struct udevice *dev)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
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struct reset_ctl rst_ctl;
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struct clk clk;
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int ret;
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priv->regs = dev_remap_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
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/* enable clock */
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ret = clk_get_by_name(dev, "hsspi", &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret < 0 && ret != -ENOSYS)
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return ret;
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ret = clk_free(&clk);
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if (ret < 0 && ret != -ENOSYS)
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return ret;
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/* get clock rate */
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ret = clk_get_by_name(dev, "pll", &clk);
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if (ret < 0 && ret != -ENOSYS)
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return ret;
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priv->clk_rate = clk_get_rate(&clk);
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ret = clk_free(&clk);
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if (ret < 0 && ret != -ENOSYS)
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return ret;
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/* perform reset */
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ret = reset_get_by_index(dev, 0, &rst_ctl);
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if (ret >= 0) {
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ret = reset_deassert(&rst_ctl);
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if (ret < 0)
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return ret;
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}
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ret = reset_free(&rst_ctl);
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if (ret < 0)
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return ret;
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/* initialize hardware */
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writel(0, priv->regs + SPI_IR_MASK_REG);
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/* clear pending interrupts */
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writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
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/* enable clk gate */
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setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
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/* read default cs polarities */
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priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
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SPI_CTL_CS_POL_MASK;
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return 0;
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}
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U_BOOT_DRIVER(bcm63xx_hsspi) = {
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.name = "bcm63xx_hsspi",
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.id = UCLASS_SPI,
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.of_match = bcm63xx_hsspi_ids,
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.ops = &bcm63xx_hsspi_ops,
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.priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
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.child_pre_probe = bcm63xx_hsspi_child_pre_probe,
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.probe = bcm63xx_hsspi_probe,
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};
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