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![Vladimir Oltean](/assets/img/avatar_default.png)
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e
("PCI: Add driver for a 'pci-host-ecam-generic' host controller")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
173 lines
5.0 KiB
C
173 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Generic PCIE host provided by e.g. QEMU
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*
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* Heavily based on drivers/pci/pcie_xilinx.c
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*
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* Copyright (C) 2016 Imagination Technologies
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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/**
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* struct generic_ecam_pcie - generic_ecam PCIe controller state
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* @cfg_base: The base address of memory mapped configuration space
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*/
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struct generic_ecam_pcie {
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void *cfg_base;
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pci_size_t size;
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int first_busno;
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};
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/**
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* pci_generic_ecam_conf_address() - Calculate the address of a config access
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @paddress: Pointer to the pointer to write the calculates address to
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*
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* Calculates the address that should be accessed to perform a PCIe
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* configuration space access for a given device identified by the PCIe
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* controller device @pcie and the bus, device & function numbers in @bdf. If
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* access to the device is not valid then the function will return an error
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* code. Otherwise the address to access will be written to the pointer pointed
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* to by @paddress.
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*/
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static int pci_generic_ecam_conf_address(const struct udevice *bus,
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pci_dev_t bdf, uint offset,
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void **paddress)
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{
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struct generic_ecam_pcie *pcie = dev_get_priv(bus);
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void *addr;
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addr = pcie->cfg_base;
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addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
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addr += PCI_DEV(bdf) << 15;
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addr += PCI_FUNC(bdf) << 12;
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addr += offset;
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*paddress = addr;
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return 0;
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}
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static bool pci_generic_ecam_addr_valid(const struct udevice *bus,
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pci_dev_t bdf)
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{
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struct generic_ecam_pcie *pcie = dev_get_priv(bus);
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int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
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return (PCI_BUS(bdf) >= pcie->first_busno &&
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PCI_BUS(bdf) < pcie->first_busno + num_buses);
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}
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/**
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* pci_generic_ecam_read_config() - Read from configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*/
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static int pci_generic_ecam_read_config(const struct udevice *bus,
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pci_dev_t bdf, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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if (!pci_generic_ecam_addr_valid(bus, bdf)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
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bdf, offset, valuep, size);
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}
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/**
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* pci_generic_ecam_write_config() - Write to configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*/
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static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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if (!pci_generic_ecam_addr_valid(bus, bdf))
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return 0;
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return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
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bdf, offset, value, size);
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}
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/**
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* pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
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* @dev: A pointer to the device being operated on
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*
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* Translate relevant data from the device tree pertaining to device @dev into
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* state that the driver will later make use of. This state is stored in the
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* device's private data structure.
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*
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* Return: 0 on success, else -EINVAL
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*/
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static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
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{
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struct generic_ecam_pcie *pcie = dev_get_priv(dev);
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struct fdt_resource reg_res;
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DECLARE_GLOBAL_DATA_PTR;
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int err;
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err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
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0, ®_res);
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if (err < 0) {
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pr_err("\"reg\" resource not found\n");
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return err;
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}
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pcie->size = fdt_resource_size(®_res);
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pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
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return 0;
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}
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static int pci_generic_ecam_probe(struct udevice *dev)
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{
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struct generic_ecam_pcie *pcie = dev_get_priv(dev);
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pcie->first_busno = dev->seq;
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return 0;
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}
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static const struct dm_pci_ops pci_generic_ecam_ops = {
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.read_config = pci_generic_ecam_read_config,
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.write_config = pci_generic_ecam_write_config,
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};
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static const struct udevice_id pci_generic_ecam_ids[] = {
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{ .compatible = "pci-host-ecam-generic" },
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{ }
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};
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U_BOOT_DRIVER(pci_generic_ecam) = {
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.name = "pci_generic_ecam",
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.id = UCLASS_PCI,
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.of_match = pci_generic_ecam_ids,
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.ops = &pci_generic_ecam_ops,
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.probe = pci_generic_ecam_probe,
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.ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
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};
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