u-boot-brain/board/freescale/p2020ds
York Sun 712cf7ab0b powerpc/mpc8xxx: Merge entries in DDR speed table
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:53 -05:00
..
ddr.c powerpc/mpc8xxx: Merge entries in DDR speed table 2011-10-09 17:57:53 -05:00
law.c powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code 2011-01-14 01:32:20 -06:00
Makefile Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
p2020ds.c tsec: Convert tsec to use PHY Lib 2011-04-20 15:09:34 -05:00
tlb.c powerpc/85xx: Enable eSDHC boot support on P2020 DS 2011-04-04 22:26:32 -05:00