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https://github.com/brain-hackers/u-boot-brain
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![Fabio Estevam](/assets/img/avatar_default.png)
Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
304 lines
7.5 KiB
C
304 lines
7.5 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6q_pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/boot_mode.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
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.gp = IMX_GPIO_NR(2, 30)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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/*
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* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
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* Compass Sensor, Accelerometer, Res Touch
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*/
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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iomux_v3_cfg_t const i2c3_pads[] = {
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MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const port_exp[] = {
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MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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}
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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gpio_direction_input(IMX_GPIO_NR(6, 15));
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return !gpio_get_value(IMX_GPIO_NR(6, 15));
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret;
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setup_iomux_enet();
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ret = cpu_eth_init(bis);
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if (ret)
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printf("FEC MXC: %s:failed\n", __func__);
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return ret;
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}
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#define BOARD_REV_B 0x200
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#define BOARD_REV_A 0x100
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static int mx6sabre_rev(void)
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{
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/*
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* Get Board ID information from OCOTP_GP1[15:8]
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* i.MX6Q ARD RevA: 0x01
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* i.MX6Q ARD RevB: 0x02
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*/
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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int reg = readl(&fuse->gp1);
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int ret;
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switch (reg >> 8 & 0x0F) {
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case 0x02:
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ret = BOARD_REV_B;
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break;
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case 0x01:
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default:
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ret = BOARD_REV_A;
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break;
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}
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return ret;
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}
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u32 get_board_rev(void)
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{
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int rev = mx6sabre_rev();
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return (get_cpu_rev() & ~(0xF << 8)) | rev;
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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/* I2C 3 Steer */
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gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
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imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
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imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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int checkboard(void)
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{
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int rev = mx6sabre_rev();
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char *revname;
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switch (rev) {
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case BOARD_REV_B:
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revname = "B";
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break;
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case BOARD_REV_A:
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default:
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revname = "A";
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break;
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}
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printf("Board: MX6Q-Sabreauto rev%s\n", revname);
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return 0;
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}
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