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https://github.com/brain-hackers/u-boot-brain
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4697abea62
Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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* (C) Copyright 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/wdt.h>
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#include <linux/err.h>
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/* Number of Watchdog Timer ticks before reset */
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#define AST_WDT_RESET_TIMEOUT 10
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#define AST_WDT_FOR_RESET 0
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static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct ast_wdt *wdt = ast_get_wdt(AST_WDT_FOR_RESET);
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u32 reset_mode = 0;
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if (IS_ERR(wdt))
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return PTR_ERR(wdt);
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switch (type) {
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case SYSRESET_WARM:
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reset_mode = WDT_CTRL_RESET_CPU;
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break;
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case SYSRESET_COLD:
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reset_mode = WDT_CTRL_RESET_CHIP;
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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/* Clear reset mode bits */
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clrsetbits_le32(&wdt->ctrl,
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(WDT_CTRL_RESET_MODE_MASK << WDT_CTRL_RESET_MODE_SHIFT),
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(reset_mode << WDT_CTRL_RESET_MODE_SHIFT));
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wdt_start(wdt, AST_WDT_RESET_TIMEOUT);
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return -EINPROGRESS;
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}
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static struct sysreset_ops ast_sysreset = {
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.request = ast_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_ast) = {
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.name = "ast_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &ast_sysreset,
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};
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