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https://github.com/brain-hackers/u-boot-brain
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f1df936445
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
18 lines
432 B
C
18 lines
432 B
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_LEVELING_H_
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#define _DDR3_TRAINING_LEVELING_H_
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#define MAX_DQ_READ_LEVELING_DELAY 15
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int ddr3_tip_print_wl_supp_result(u32 dev_num);
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int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
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u32 *cs_mask);
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u32 hws_ddr3_tip_max_cs_get(void);
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#endif /* _DDR3_TRAINING_LEVELING_H_ */
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