mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 20:39:43 +09:00
f1df936445
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
350 lines
12 KiB
C
350 lines
12 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_FLOW_H_
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#define _DDR3_TRAINING_IP_FLOW_H_
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#include "ddr3_training_ip.h"
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#include "ddr3_training_ip_pbs.h"
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#define MRS0_CMD 0x3
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#define MRS1_CMD 0x4
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#define MRS2_CMD 0x8
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#define MRS3_CMD 0x9
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/*
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* Definitions of INTERFACE registers
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*/
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#define READ_BUFFER_SELECT 0x14a4
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/*
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* Definitions of PHY registers
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*/
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#define KILLER_PATTERN_LENGTH 32
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#define EXT_ACCESS_BURST_LENGTH 8
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#define IS_ACTIVE(if_mask , if_id) \
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((if_mask) & (1 << (if_id)))
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#define VALIDATE_ACTIVE(mask, id) \
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{ \
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if (IS_ACTIVE(mask, id) == 0) \
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continue; \
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}
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#define GET_TOPOLOGY_NUM_OF_BUSES() \
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(ddr3_get_topology_map()->num_of_bus_per_interface)
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#define DDR3_IS_ECC_PUP3_MODE(if_mask) \
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(((if_mask) == 0xb) ? 1 : 0)
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#define DDR3_IS_ECC_PUP4_MODE(if_mask) \
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(((((if_mask) & 0x10) == 0)) ? 0 : 1)
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#define DDR3_IS_16BIT_DRAM_MODE(mask) \
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(((((mask) & 0x4) == 0)) ? 1 : 0)
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#define MEGA 1000000
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#define BUS_WIDTH_IN_BITS 8
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/*
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* DFX address Space
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* Table 2: DFX address space
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* Address Bits Value Description
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* [31 : 20] 0x? DFX base address bases PCIe mapping
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* [19 : 15] 0...Number_of_client-1 Client Index inside pipe.
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* See also Table 1 Multi_cast = 29 Broadcast = 28
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* [14 : 13] 2'b01 Access to Client Internal Register
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* [12 : 0] Client Internal Register offset See related Client Registers
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* [14 : 13] 2'b00 Access to Ram Wrappers Internal Register
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* [12 : 6] 0 Number_of_rams-1 Ram Index inside Client
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* [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers
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* Registers
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*/
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/* nsec */
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#define TREFI_LOW 7800
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#define TREFI_HIGH 3900
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#define TR2R_VALUE_REG 0x180
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#define TR2R_MASK_REG 0x180
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#define TRFC_MASK_REG 0x7f
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#define TR2W_MASK_REG 0x600
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#define TW2W_HIGH_VALUE_REG 0x1800
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#define TW2W_HIGH_MASK_REG 0xf800
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#define TRFC_HIGH_VALUE_REG 0x20000
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#define TRFC_HIGH_MASK_REG 0x70000
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#define TR2R_HIGH_VALUE_REG 0x0
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#define TR2R_HIGH_MASK_REG 0x380000
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#define TMOD_VALUE_REG 0x16000000
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#define TMOD_MASK_REG 0x1e000000
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#define T_VALUE_REG 0x40000000
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#define T_MASK_REG 0xc0000000
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#define AUTO_ZQC_TIMING 15384
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#define WRITE_XBAR_PORT1 0xc03f8077
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#define READ_XBAR_PORT1 0xc03f8073
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#define DISABLE_DDR_TUNING_DATA 0x02294285
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#define ENABLE_DDR_TUNING_DATA 0x12294285
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#define ODPG_TRAINING_STATUS_REG 0x18488
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#define ODPG_TRAINING_TRIGGER_REG 0x1030
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#define ODPG_STATUS_DONE_REG 0x16fc
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#define ODPG_ENABLE_REG 0x186d4
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#define ODPG_ENABLE_OFFS 0
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#define ODPG_DISABLE_OFFS 8
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#define ODPG_TRAINING_CONTROL_REG 0x1034
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#define ODPG_OBJ1_OPCODE_REG 0x103c
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#define ODPG_OBJ1_ITER_CNT_REG 0x10b4
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#define CALIB_OBJ_PRFA_REG 0x10c4
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#define ODPG_WRITE_LEVELING_DONE_CNTR_REG 0x10f8
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#define ODPG_WRITE_READ_MODE_ENABLE_REG 0x10fc
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#define TRAINING_OPCODE_1_REG 0x10b4
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#define SDRAM_CONFIGURATION_REG 0x1400
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#define DDR_CONTROL_LOW_REG 0x1404
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#define SDRAM_TIMING_LOW_REG 0x1408
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#define SDRAM_TIMING_HIGH_REG 0x140c
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#define SDRAM_ACCESS_CONTROL_REG 0x1410
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#define SDRAM_OPEN_PAGE_CONTROL_REG 0x1414
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#define SDRAM_OPERATION_REG 0x1418
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#define DUNIT_CONTROL_HIGH_REG 0x1424
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#define ODT_TIMING_LOW 0x1428
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#define DDR_TIMING_REG 0x142c
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#define ODT_TIMING_HI_REG 0x147c
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#define SDRAM_INIT_CONTROL_REG 0x1480
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#define SDRAM_ODT_CONTROL_HIGH_REG 0x1498
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#define DUNIT_ODT_CONTROL_REG 0x149c
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#define READ_BUFFER_SELECT_REG 0x14a4
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#define DUNIT_MMASK_REG 0x14b0
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#define CALIB_MACHINE_CTRL_REG 0x14cc
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#define DRAM_DLL_TIMING_REG 0x14e0
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#define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4
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#define DRAM_ZQ_TIMING_REG 0x14e8
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#define DFS_REG 0x1528
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#define READ_DATA_SAMPLE_DELAY 0x1538
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#define READ_DATA_READY_DELAY 0x153c
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#define TRAINING_REG 0x15b0
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#define TRAINING_SW_1_REG 0x15b4
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#define TRAINING_SW_2_REG 0x15b8
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#define TRAINING_PATTERN_BASE_ADDRESS_REG 0x15bc
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#define TRAINING_DBG_1_REG 0x15c0
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#define TRAINING_DBG_2_REG 0x15c4
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#define TRAINING_DBG_3_REG 0x15c8
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#define RANK_CTRL_REG 0x15e0
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#define TIMING_REG 0x15e4
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#define DRAM_PHY_CONFIGURATION 0x15ec
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#define MR0_REG 0x15d0
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#define MR1_REG 0x15d4
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#define MR2_REG 0x15d8
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#define MR3_REG 0x15dc
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#define TIMING_REG 0x15e4
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#define ODPG_CTRL_CONTROL_REG 0x1600
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#define ODPG_DATA_CONTROL_REG 0x1630
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#define ODPG_PATTERN_ADDR_OFFSET_REG 0x1638
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#define ODPG_DATA_BUF_SIZE_REG 0x163c
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#define PHY_LOCK_STATUS_REG 0x1674
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#define PHY_REG_FILE_ACCESS 0x16a0
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#define TRAINING_WRITE_LEVELING_REG 0x16ac
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#define ODPG_PATTERN_ADDR_REG 0x16b0
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#define ODPG_PATTERN_DATA_HI_REG 0x16b4
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#define ODPG_PATTERN_DATA_LOW_REG 0x16b8
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#define ODPG_BIST_LAST_FAIL_ADDR_REG 0x16bc
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#define ODPG_BIST_DATA_ERROR_COUNTER_REG 0x16c0
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#define ODPG_BIST_FAILED_DATA_HI_REG 0x16c4
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#define ODPG_BIST_FAILED_DATA_LOW_REG 0x16c8
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#define ODPG_WRITE_DATA_ERROR_REG 0x16cc
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#define CS_ENABLE_REG 0x16d8
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#define WR_LEVELING_DQS_PATTERN_REG 0x16dc
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#define ODPG_BIST_DONE 0x186d4
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#define ODPG_BIST_DONE_BIT_OFFS 0
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#define ODPG_BIST_DONE_BIT_VALUE 0
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#define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830
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#define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834
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#define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838
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#define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c
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#define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0
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#define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4
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#define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8
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#define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc
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#define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0
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#define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4
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#define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8
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#define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc
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#define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0
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#define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4
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#define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8
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#define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc
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#define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930
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#define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934
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#define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938
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#define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c
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#define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0
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#define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4
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#define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8
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#define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc
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#define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0
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#define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4
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#define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8
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#define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc
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#define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0
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#define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4
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#define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8
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#define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc
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#define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30
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#define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34
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#define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38
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#define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c
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#define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0
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#define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4
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#define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8
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#define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc
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#define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0
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#define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4
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#define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8
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#define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc
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#define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0
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#define WL_PHY_REG 0x0
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#define WRITE_CENTRALIZATION_PHY_REG 0x1
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#define RL_PHY_REG 0x2
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#define READ_CENTRALIZATION_PHY_REG 0x3
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#define PBS_RX_PHY_REG 0x50
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#define PBS_TX_PHY_REG 0x10
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#define PHY_CONTROL_PHY_REG 0x90
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#define BW_PHY_REG 0x92
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#define RATE_PHY_REG 0x94
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#define CMOS_CONFIG_PHY_REG 0xa2
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#define PAD_ZRI_CALIB_PHY_REG 0xa4
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#define PAD_ODT_CALIB_PHY_REG 0xa6
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#define PAD_CONFIG_PHY_REG 0xa8
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#define PAD_PRE_DISABLE_PHY_REG 0xa9
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#define TEST_ADLL_REG 0xbf
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#define CSN_IOB_VREF_REG(cs) (0xdb + (cs * 12))
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#define CSN_IO_BASE_VREF_REG(cs) (0xd0 + (cs * 12))
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#define RESULT_DB_PHY_REG_ADDR 0xc0
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#define RESULT_DB_PHY_REG_RX_OFFSET 5
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#define RESULT_DB_PHY_REG_TX_OFFSET 0
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/* TBD - for NP5 use only CS 0 */
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#define PHY_WRITE_DELAY(cs) WL_PHY_REG
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/*( ( _cs_ == 0 ) ? 0x0 : 0x4 )*/
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/* TBD - for NP5 use only CS 0 */
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#define PHY_READ_DELAY(cs) RL_PHY_REG
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#define DDR0_ADDR_1 0xf8258
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#define DDR0_ADDR_2 0xf8254
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#define DDR1_ADDR_1 0xf8270
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#define DDR1_ADDR_2 0xf8270
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#define DDR2_ADDR_1 0xf825c
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#define DDR2_ADDR_2 0xf825c
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#define DDR3_ADDR_1 0xf8264
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#define DDR3_ADDR_2 0xf8260
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#define DDR4_ADDR_1 0xf8274
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#define DDR4_ADDR_2 0xf8274
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#define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
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#define GET_BLOCK_ID_MAX_FREQ(dev_num, block_id) 800000
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#define CS0_RD_LVL_REF_DLY_OFFS 0
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#define CS0_RD_LVL_REF_DLY_LEN 0
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#define CS0_RD_LVL_PH_SEL_OFFS 0
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#define CS0_RD_LVL_PH_SEL_LEN 0
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#define CS_REGISTER_ADDR_OFFSET 4
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#define CALIBRATED_OBJECTS_REG_ADDR_OFFSET 0x10
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#define MAX_POLLING_ITERATIONS 100000
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#define PHASE_REG_OFFSET 32
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#define NUM_BYTES_IN_BURST 31
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#define NUM_OF_CS 4
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#define CS_REG_VALUE(cs_num) (cs_mask_reg[cs_num])
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#define ADLL_LENGTH 32
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struct write_supp_result {
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enum hws_wl_supp stage;
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int is_pup_fail;
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};
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struct page_element {
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enum hws_page_size page_size_8bit;
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/* page size in 8 bits bus width */
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enum hws_page_size page_size_16bit;
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/* page size in 16 bits bus width */
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u32 ui_page_mask;
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/* Mask used in register */
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};
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int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
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enum hws_ddr_freq frequency,
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u32 *round_trip_delay_arr);
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int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
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enum hws_ddr_freq frequency,
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u32 *total_round_trip_delay_arr);
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int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
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int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, u32 exp_value, u32 mask, u32 offset,
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u32 poll_tries);
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int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 *data, u32 mask);
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int ddr3_tip_bus_read_modify_write(u32 dev_num,
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enum hws_access_type access_type,
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u32 if_id, u32 phy_id,
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enum hws_ddr_phy phy_type,
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u32 reg_addr, u32 data_value, u32 reg_mask);
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int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
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u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
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u32 *data);
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int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
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u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
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enum hws_ddr_phy e_phy_type, u32 reg_addr,
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u32 data_value);
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int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
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enum hws_ddr_freq memory_freq);
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int ddr3_tip_adjust_dqs(u32 dev_num);
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int ddr3_tip_init_controller(u32 dev_num);
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int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
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u32 num_of_bursts, u32 *addr);
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int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
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u32 num_of_bursts, u32 *addr);
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int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
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int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
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int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
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int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
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int ddr3_tip_dynamic_write_leveling(u32 dev_num);
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int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
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int ddr3_tip_static_init_controller(u32 dev_num);
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int ddr3_tip_configure_phy(u32 dev_num);
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int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, enum hws_pattern pattern,
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u32 load_addr);
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int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
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int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, enum hws_dir direction, u32 tx_phases,
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u32 tx_burst_size, u32 rx_phases,
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u32 delay_between_burst, u32 rd_mode, u32 cs_num,
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u32 addr_stress_jump, u32 single_pattern);
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int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value);
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int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd, u32 data,
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u32 mask);
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int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
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int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id);
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int ddr3_tip_reset_fifo_ptr(u32 dev_num);
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int read_pup_value(int pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
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int reg_addr, u32 mask);
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int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
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int reg_addr, u32 mask);
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int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
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int reg_addr);
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int ddr3_tip_tune_training_params(u32 dev_num,
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struct tune_train_params *params);
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#endif /* _DDR3_TRAINING_IP_FLOW_H_ */
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