mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 20:39:43 +09:00
f1df936445
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
653 lines
13 KiB
C
653 lines
13 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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/* List of allowed frequency listed in order of enum hws_ddr_freq */
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u32 freq_val[DDR_FREQ_LIMIT] = {
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0, /*DDR_FREQ_LOW_FREQ */
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400, /*DDR_FREQ_400, */
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533, /*DDR_FREQ_533, */
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666, /*DDR_FREQ_667, */
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800, /*DDR_FREQ_800, */
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933, /*DDR_FREQ_933, */
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1066, /*DDR_FREQ_1066, */
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311, /*DDR_FREQ_311, */
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333, /*DDR_FREQ_333, */
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467, /*DDR_FREQ_467, */
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850, /*DDR_FREQ_850, */
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600, /*DDR_FREQ_600 */
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300, /*DDR_FREQ_300 */
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900, /*DDR_FREQ_900 */
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360, /*DDR_FREQ_360 */
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1000 /*DDR_FREQ_1000 */
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};
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/* Table for CL values per frequency for each speed bin index */
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struct cl_val_per_freq cas_latency_table[] = {
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/*
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* 400M 667M 933M 311M 467M 600M 360
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* 100M 533M 800M 1066M 333M 850M 900
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* 1000 (the order is 100, 400, 533 etc.)
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*/
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/* DDR3-800D */
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{ {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-800E */
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{ {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1066E */
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{ {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} },
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/* DDR3-1066F */
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{ {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1066G */
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{ {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1333F* */
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{ {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333G */
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{ {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} },
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/* DDR3-1333H */
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{ {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1333J* */
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{ {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0}
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/* DDR3-1600G* */},
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{ {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600H */
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{ {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} },
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/* DDR3-1600J */
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{ {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} },
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/* DDR3-1600K */
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{ {6, 6, 8, 10, 11, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0 } },
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/* DDR3-1866J* */
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{ {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} },
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/* DDR3-1866K */
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{ {6, 5, 7, 8, 10, 11, 0, 5, 5, 7, 11, 8, 5, 11, 5, 11} },
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/* DDR3-1866L */
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{ {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} },
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/* DDR3-1866M* */
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{ {6, 6, 8, 10, 11, 13, 0, 6, 6, 8, 13, 10, 6, 13, 6, 13} },
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/* DDR3-2133K* */
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{ {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} },
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/* DDR3-2133L */
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{ {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} },
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/* DDR3-2133M */
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{ {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} },
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/* DDR3-2133N* */
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{ {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} },
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/* DDR3-1333H-ext */
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{ {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1600K-ext */
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{ {6, 6, 7, 9, 11, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1866M-ext */
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{ {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} },
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};
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/* Table for CWL values per speedbin index */
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struct cl_val_per_freq cas_write_latency_table[] = {
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/*
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* 400M 667M 933M 311M 467M 600M 360
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* 100M 533M 800M 1066M 333M 850M 900
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* (the order is 100, 400, 533 etc.)
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*/
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/* DDR3-800D */
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{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-800E */
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{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-1066E */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1066F */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1066G */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333F* */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333G */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333H */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333J* */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600G* */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600H */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600J */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600K */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1866J* */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
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/* DDR3-1866K */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
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/* DDR3-1866L */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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/* DDR3-1866M* */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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/* DDR3-2133K* */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133L */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133M */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133N* */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-1333H-ext */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600K-ext */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1866M-ext */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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};
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u8 twr_mask_table[] = {
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10,
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10,
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10,
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10,
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10,
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1, /*5 */
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2, /*6 */
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3, /*7 */
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10,
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10,
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5, /*10 */
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10,
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6, /*12 */
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10,
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7, /*14 */
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10,
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0 /*16 */
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};
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u8 cl_mask_table[] = {
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0,
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0,
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0,
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0,
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0,
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0x2,
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0x4,
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0x6,
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0x8,
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0xa,
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0xc,
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0xe,
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0x1,
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0x3,
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0x5,
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0x5
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};
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u8 cwl_mask_table[] = {
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0,
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0,
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0,
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0,
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0,
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0,
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0x1,
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0x2,
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0x3,
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0x4,
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0x5,
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0x6,
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0x7,
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0x8,
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0x9,
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0x9
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};
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/* RFC values (in ns) */
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u16 rfc_table[] = {
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90, /* 512M */
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110, /* 1G */
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160, /* 2G */
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260, /* 4G */
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350 /* 8G */
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};
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u32 speed_bin_table_t_rc[] = {
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50000,
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52500,
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48750,
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50625,
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52500,
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46500,
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48000,
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49500,
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51000,
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45000,
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46250,
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47500,
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48750,
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44700,
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45770,
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46840,
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47910,
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43285,
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44220,
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45155,
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46900
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};
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u32 speed_bin_table_t_rcd_t_rp[] = {
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12500,
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15000,
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11250,
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13125,
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15000,
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10500,
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12000,
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13500,
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15000,
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10000,
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11250,
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12500,
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13750,
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10700,
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11770,
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12840,
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13910,
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10285,
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11022,
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12155,
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13090,
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};
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enum {
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PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR = 0,
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PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM
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};
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static u8 pattern_killer_pattern_table_map[KILLER_PATTERN_LENGTH * 2][2] = {
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/*Aggressor / Victim */
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{1, 0},
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{0, 0},
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{1, 0},
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{1, 1},
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{0, 1},
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{0, 1},
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{1, 0},
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{0, 1},
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{1, 0},
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{0, 1},
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{1, 0},
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{1, 0},
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{0, 1},
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{1, 0},
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{0, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{1, 0},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{0, 0},
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{0, 0},
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{0, 1},
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{0, 1},
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{1, 1},
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{0, 0},
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{0, 0},
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{1, 1},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{1, 1},
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{0, 0},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 1},
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{0, 0},
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{0, 1},
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{0, 1},
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{0, 0},
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{1, 1},
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{1, 1},
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{1, 0},
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{1, 0},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1}
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};
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static u8 pattern_vref_pattern_table_map[] = {
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/* 1 means 0xffffffff, 0 is 0x0 */
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0xb8,
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0x52,
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0x55,
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0x8a,
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0x33,
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0xa6,
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0x6d,
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0xfe
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};
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/* Return speed Bin value for selected index and t* element */
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u32 speed_bin_table(u8 index, enum speed_bin_table_elements element)
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{
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u32 result = 0;
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switch (element) {
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case SPEED_BIN_TRCD:
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case SPEED_BIN_TRP:
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result = speed_bin_table_t_rcd_t_rp[index];
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break;
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case SPEED_BIN_TRAS:
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if (index < 6)
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result = 37500;
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else if (index < 10)
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result = 36000;
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else if (index < 14)
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result = 35000;
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else if (index < 18)
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result = 34000;
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else
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result = 33000;
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break;
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case SPEED_BIN_TRC:
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result = speed_bin_table_t_rc[index];
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break;
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case SPEED_BIN_TRRD1K:
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if (index < 3)
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result = 10000;
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else if (index < 6)
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result = 7005;
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else if (index < 14)
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result = 6000;
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else
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result = 5000;
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break;
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case SPEED_BIN_TRRD2K:
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if (index < 6)
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result = 10000;
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else if (index < 14)
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result = 7005;
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else
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result = 6000;
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break;
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case SPEED_BIN_TPD:
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if (index < 3)
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result = 7500;
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else if (index < 10)
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result = 5625;
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else
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result = 5000;
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break;
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case SPEED_BIN_TFAW1K:
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if (index < 3)
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result = 40000;
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else if (index < 6)
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result = 37500;
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else if (index < 14)
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result = 30000;
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else if (index < 18)
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result = 27000;
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else
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result = 25000;
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break;
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case SPEED_BIN_TFAW2K:
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if (index < 6)
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result = 50000;
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else if (index < 10)
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result = 45000;
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else if (index < 14)
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result = 40000;
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else
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result = 35000;
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break;
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case SPEED_BIN_TWTR:
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result = 7500;
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break;
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case SPEED_BIN_TRTP:
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result = 7500;
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break;
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case SPEED_BIN_TWR:
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result = 15000;
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break;
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case SPEED_BIN_TMOD:
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result = 15000;
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break;
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default:
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break;
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}
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return result;
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}
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static inline u32 pattern_table_get_killer_word(u8 dqs, u8 index)
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{
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u8 i, byte = 0;
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u8 role;
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for (i = 0; i < 8; i++) {
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role = (i == dqs) ?
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(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
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(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
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byte |= pattern_killer_pattern_table_map[index][role] << i;
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}
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return byte | (byte << 8) | (byte << 16) | (byte << 24);
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}
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static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index)
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{
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u8 i, byte0 = 0, byte1 = 0;
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u8 role;
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for (i = 0; i < 8; i++) {
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role = (i == dqs) ?
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(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
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(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
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byte0 |= pattern_killer_pattern_table_map[index * 2][role] << i;
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}
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for (i = 0; i < 8; i++) {
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role = (i == dqs) ?
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(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
|
|
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
|
|
byte1 |= pattern_killer_pattern_table_map
|
|
[index * 2 + 1][role] << i;
|
|
}
|
|
|
|
return byte0 | (byte0 << 8) | (byte1 << 16) | (byte1 << 24);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_word(u8 sso, u8 index)
|
|
{
|
|
u8 step = sso + 1;
|
|
|
|
if (0 == ((index / step) & 1))
|
|
return 0x0;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_vref_word(u8 index)
|
|
{
|
|
if (0 == ((pattern_vref_pattern_table_map[index / 8] >>
|
|
(index % 8)) & 1))
|
|
return 0x0;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_vref_word16(u8 index)
|
|
{
|
|
if (0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0x00000000;
|
|
else if (1 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0xffff0000;
|
|
else if (0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
1 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0x0000ffff;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_static_pbs_word(u8 index)
|
|
{
|
|
u16 temp;
|
|
|
|
temp = ((0x00ff << (index / 3)) & 0xff00) >> 8;
|
|
|
|
return temp | (temp << 8) | (temp << 16) | (temp << 24);
|
|
}
|
|
|
|
inline u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
|
|
{
|
|
u32 pattern;
|
|
struct hws_topology_map *tm = ddr3_get_topology_map();
|
|
|
|
if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) {
|
|
/* 32bit patterns */
|
|
switch (type) {
|
|
case PATTERN_PBS1:
|
|
case PATTERN_PBS2:
|
|
if (index == 0 || index == 2 || index == 5 ||
|
|
index == 7)
|
|
pattern = PATTERN_55;
|
|
else
|
|
pattern = PATTERN_AA;
|
|
break;
|
|
case PATTERN_PBS3:
|
|
if (0 == (index & 1))
|
|
pattern = PATTERN_55;
|
|
else
|
|
pattern = PATTERN_AA;
|
|
break;
|
|
case PATTERN_RL:
|
|
if (index < 6)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_80;
|
|
break;
|
|
case PATTERN_STATIC_PBS:
|
|
pattern = pattern_table_get_static_pbs_word(index);
|
|
break;
|
|
case PATTERN_KILLER_DQ0:
|
|
case PATTERN_KILLER_DQ1:
|
|
case PATTERN_KILLER_DQ2:
|
|
case PATTERN_KILLER_DQ3:
|
|
case PATTERN_KILLER_DQ4:
|
|
case PATTERN_KILLER_DQ5:
|
|
case PATTERN_KILLER_DQ6:
|
|
case PATTERN_KILLER_DQ7:
|
|
pattern = pattern_table_get_killer_word(
|
|
(u8)(type - PATTERN_KILLER_DQ0), index);
|
|
break;
|
|
case PATTERN_RL2:
|
|
if (index < 6)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_01;
|
|
break;
|
|
case PATTERN_TEST:
|
|
if (index > 1 && index < 6)
|
|
pattern = PATTERN_20;
|
|
else
|
|
pattern = PATTERN_00;
|
|
break;
|
|
case PATTERN_FULL_SSO0:
|
|
case PATTERN_FULL_SSO1:
|
|
case PATTERN_FULL_SSO2:
|
|
case PATTERN_FULL_SSO3:
|
|
pattern = pattern_table_get_sso_word(
|
|
(u8)(type - PATTERN_FULL_SSO0), index);
|
|
break;
|
|
case PATTERN_VREF:
|
|
pattern = pattern_table_get_vref_word(index);
|
|
break;
|
|
default:
|
|
pattern = 0;
|
|
break;
|
|
}
|
|
} else {
|
|
/* 16bit patterns */
|
|
switch (type) {
|
|
case PATTERN_PBS1:
|
|
case PATTERN_PBS2:
|
|
case PATTERN_PBS3:
|
|
pattern = PATTERN_55AA;
|
|
break;
|
|
case PATTERN_RL:
|
|
if (index < 3)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_80;
|
|
break;
|
|
case PATTERN_STATIC_PBS:
|
|
pattern = PATTERN_00FF;
|
|
break;
|
|
case PATTERN_KILLER_DQ0:
|
|
case PATTERN_KILLER_DQ1:
|
|
case PATTERN_KILLER_DQ2:
|
|
case PATTERN_KILLER_DQ3:
|
|
case PATTERN_KILLER_DQ4:
|
|
case PATTERN_KILLER_DQ5:
|
|
case PATTERN_KILLER_DQ6:
|
|
case PATTERN_KILLER_DQ7:
|
|
pattern = pattern_table_get_killer_word16(
|
|
(u8)(type - PATTERN_KILLER_DQ0), index);
|
|
break;
|
|
case PATTERN_RL2:
|
|
if (index < 3)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_01;
|
|
break;
|
|
case PATTERN_TEST:
|
|
pattern = PATTERN_0080;
|
|
break;
|
|
case PATTERN_FULL_SSO0:
|
|
pattern = 0x0000ffff;
|
|
break;
|
|
case PATTERN_FULL_SSO1:
|
|
case PATTERN_FULL_SSO2:
|
|
case PATTERN_FULL_SSO3:
|
|
pattern = pattern_table_get_sso_word(
|
|
(u8)(type - PATTERN_FULL_SSO1), index);
|
|
break;
|
|
case PATTERN_VREF:
|
|
pattern = pattern_table_get_vref_word16(index);
|
|
break;
|
|
default:
|
|
pattern = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return pattern;
|
|
}
|