mirror of
https://github.com/brain-hackers/u-boot-brain
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526cbff292
Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet_serdes.h"
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
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NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
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[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
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[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
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PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
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SATA2, NONE, NONE, NONE, NONE, },
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[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
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PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
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NONE, NONE, NONE, NONE, NONE, NONE, },
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[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
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PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
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PCIE3, NONE, NONE, NONE, NONE, },
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[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
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SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
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[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
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PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
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NONE, NONE, NONE, },
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[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
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NONE, NONE, NONE, },
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[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
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NONE, NONE, NONE, NONE, NONE, },
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[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
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PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
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NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
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[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
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SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
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NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
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[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
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SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
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};
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
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{
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if (!serdes_lane_enabled(lane))
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return NONE;
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(u32 prtcl)
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{
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int i;
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if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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