Simon Glass d1cd045982 x86: Emit post codes in startup code for Chromebooks ... On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2014-11-21 07:34:11 +01:00
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car.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
coreboot.c	x86: Emit post codes in startup code for Chromebooks	2014-11-21 07:34:11 +01:00
ipchecksum.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00
Makefile	x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory	2014-11-21 07:24:12 +01:00
pci.c	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
sdram.c	x86: Fix up some missing prototypes	2014-11-21 07:24:09 +01:00
tables.c	SPDX-License-Identifier: convert BSD-3-Clause files	2013-08-19 15:45:35 -04:00
timestamp.c	x86: Support adding coreboot timestanps to bootstage	2013-05-13 13:33:22 -07:00