mirror of
https://github.com/brain-hackers/u-boot-brain
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70a09c6c3d
Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
73 lines
1.7 KiB
Plaintext
73 lines
1.7 KiB
Plaintext
menu "x86 architecture"
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depends on X86
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config SYS_ARCH
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default "x86"
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config USE_PRIVATE_LIBGCC
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default y
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choice
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prompt "Target select"
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config TARGET_COREBOOT
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bool "Support coreboot"
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help
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This target is used for running U-Boot on top of Coreboot. In
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this case Coreboot does the early inititalisation, and U-Boot
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takes over once the RAM, video and CPU are fully running.
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U-Boot is loaded as a fallback payload from Coreboot, in
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Coreboot terminology. This method was used for the Chromebook
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Pixel when launched.
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config TARGET_CHROMEBOOK_LINK
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bool "Support Chromebook link"
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help
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This is the Chromebook Pixel released in 2013. It uses an Intel
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i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
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SDRAM. It has a Panther Point platform controller hub, PCIe
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WiFi and Bluetooth. It also includes a 720p webcam, USB SD
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reader, microphone and speakers, display port and 32GB SATA
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solid state drive. There is a Chrome OS EC connected on LPC,
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and it provides a 2560x1700 high resolution touch-enabled LCD
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display.
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endchoice
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config RAMBASE
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hex
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default 0x100000
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config RAMTOP
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hex
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default 0x200000
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config XIP_ROM_SIZE
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hex
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default 0x10000
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config CPU_ADDR_BITS
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int
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default 36
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config ROM_SIZE
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hex
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default 0x800000
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config HAVE_INTEL_ME
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bool "Platform requires Intel Management Engine"
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help
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Newer higher-end devices have an Intel Management Engine (ME)
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which is a very large binary blob (typically 1.5MB) which is
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required for the platform to work. This enforces a particular
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SPI flash format. You will need to supply the me.bin file in
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your board directory.
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "board/chromebook-x86/coreboot/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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endmenu
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