mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
709ea543b9
At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.
For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.
Instead, add a stdio_dev pointer to each of the stdio member functions.
Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.
Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.
22: stdio: Pass device pointer to stdio methods
arm: (for 2/2 boards) all +244.0 bss -4.0 text +248.0
powerpc: (for 1/1 boards) all +428.0 text +428.0
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
338 lines
10 KiB
C
338 lines
10 KiB
C
/*
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* (C) Copyright 2002 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define GTREGREAD(x) 0xffffffff /* needed for debug */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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/* these hardware addresses are pretty bogus, please change them to
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suit your needs */
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/* first ethernet */
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#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
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#define CONFIG_IPADDR 192.168.0.105
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#define CONFIG_SERVERIP 192.168.0.100
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#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
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#define CONFIG_BAUDRATE 9600 /* console baudrate */
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#undef CONFIG_WATCHDOG
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp 1000000; " \
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"setenv bootargs root=ramfs console=ttyS00,9600 " \
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"ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
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"${netmask}:${hostname}:eth0:none; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_JFFS2
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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/*
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* choose between COM1 and COM2 as serial console
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*/
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#define CONFIG_CONS_INDEX 1
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_BOARD_ASM_INIT
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#define CONFIG_MISC_INIT_R
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/*
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* Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
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*/
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#undef CONFIG_SYS_ADDRESS_MAP_A
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#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
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#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
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#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
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#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
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#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
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#define CONFIG_SYS_PCI_IO_BUS 0x00800000
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#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
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#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
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#define CONFIG_SYS_ISA_IO_BUS 0x00000000
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#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
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#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
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/* driver defines FDC,IDE,... */
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_USR_LED_BASE 0x78000000
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#define CONFIG_SYS_NVRAM_BASE 0xff000000
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#define CONFIG_SYS_UART_BASE 0xff400000
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#define CONFIG_SYS_FLASH_BASE 0xfff00000
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#define MPC107_EUMB_ADDR 0xfce00000
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#define MPC107_EUMB_PI 0xfce41090
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#define MPC107_EUMB_GCR 0xfce41020
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#define MPC107_EUMB_IACKR 0xfce600a0
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#define MPC107_I2C_ADDR 0xfce03000
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/*
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Flash mapping/organization on the MPC10x.
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*/
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#define FLASH_BASE0_PRELIM 0xff800000
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#define FLASH_BASE1_PRELIM 0xffc00000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_CMD_MTDPARTS
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#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
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#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
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#undef CONFIG_SYS_MEMTEST
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
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#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
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#define CONFIG_ENV_ADDR 0x0
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#define CONFIG_ENV_MAP_ADRS 0xff000000
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#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
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#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
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#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
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/*
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* Serial devices
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 24000000
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8)
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/*
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* PCI stuff
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_PNP /* pci plug-and-play */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO
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#undef CONFIG_PCI_SCAN_SHOW
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/*
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* Optional Video console (graphic: SMI LynxEM)
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*/
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#define CONFIG_VIDEO
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#define CONFIG_CFB_CONSOLE
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#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
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#define VIDEO_TSTC_FCT serial_stub_tstc
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#define VIDEO_GETC_FCT serial_stub_getc
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#define CONFIG_VIDEO_SMI_LYNXEM
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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/*
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* Initial BATs
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*/
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#if 1
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#define CONFIG_SYS_IBAT0L 0
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#define CONFIG_SYS_IBAT0U 0
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_IBAT1L 0
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#define CONFIG_SYS_IBAT1U 0
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_IBAT2L 0
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#define CONFIG_SYS_IBAT2U 0
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_IBAT3L 0
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#define CONFIG_SYS_IBAT3U 0
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#else
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/* SDRAM */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
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/* address range for flashes */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* ISA IO space */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* ISA memory space */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#endif
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/*
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* Speed settings are board specific
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*/
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#define CONFIG_SYS_BUS_CLK 100000000
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#define CONFIG_SYS_CPU_CLK 400000000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* L2CR setup -- make sure this is right for your board!
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* look in include/74xx_7xx.h for the defines used here
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*/
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#define CONFIG_SYS_L2
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#if 1
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#define L2_INIT 0 /* cpu 750 CXe*/
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#else
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#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#endif
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_EEPRO100_SROM_WRITE
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#endif /* __CONFIG_H */
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