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![Lukasz Majewski](/assets/img/avatar_default.png)
After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79106
The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
140 lines
2.8 KiB
Plaintext
140 lines
2.8 KiB
Plaintext
/*
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* Copyright 2018
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx53.dtsi"
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#include "imx53-pinfunc.h"
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/ {
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model = "K+P iMX53";
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compatible = "kp,imx53-kp", "fsl,imx53";
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chosen {
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stdout-path = &uart2;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eth>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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clock_frequency = <100000>;
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scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic: mc34708@8 {
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compatible = "fsl,mc34708";
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reg = <0x8>;
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};
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};
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&i2c3 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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clock_frequency = <100000>;
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scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-kp {
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pinctrl_eth: ethgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
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MX53_PAD_FEC_MDC__FEC_MDC 0x4
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
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/* The RX_ER pin needs to be pull down */
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/* for this device */
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* PHY RESET */
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MX53_PAD_PATA_DA_0__GPIO7_6 0x182
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/* VBUS_PWR_EN */
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MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
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/* BOOSTER_OFF */
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MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
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/* LCD BACKLIGHT */
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MX53_PAD_GPIO_1__GPIO1_1 0x1e4
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/* KEY1 GPIO */
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MX53_PAD_EIM_RW__GPIO2_26 0x1e4
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__I2C2_SDA
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(0x1ee | IMX_PAD_SION)
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MX53_PAD_KEY_COL3__I2C2_SCL
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(0x1ee | IMX_PAD_SION)
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>;
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};
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pinctrl_i2c2_gpio: i2c2grpgpio {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
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MX53_PAD_KEY_COL3__GPIO4_12 0x1e4
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION)
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MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION)
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>;
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};
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pinctrl_i2c3_gpio: i2c3grpgpio {
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fsl,pins = <
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MX53_PAD_GPIO_6__GPIO1_6 0x1e4
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MX53_PAD_GPIO_5__GPIO1_5 0x1e4
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
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>;
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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