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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
362 lines
9.2 KiB
C
362 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/arch/scu.h>
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#include <asm/pl310.h>
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#include <dt-bindings/reset/altr,rst-mgr.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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static struct nic301_registers *nic301_regs =
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(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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static struct scu_registers *scu_regs =
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(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
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/*
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* DesignWare Ethernet initialization
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*/
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#ifdef CONFIG_ETH_DESIGNWARE
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void dwmac_deassert_reset(const unsigned int of_reset_id,
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const u32 phymode)
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{
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u32 physhift, reset;
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if (of_reset_id == EMAC0_RESET) {
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physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
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reset = SOCFPGA_RESET(EMAC0);
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} else if (of_reset_id == EMAC1_RESET) {
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physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
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reset = SOCFPGA_RESET(EMAC1);
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} else {
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printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
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return;
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}
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/* configure to PHY interface select choosed */
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clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
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SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
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phymode << physhift);
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/* Release the EMAC controller from reset */
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socfpga_per_reset(reset, 0);
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}
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static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
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{
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if (!phymode)
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return -EINVAL;
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if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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return 0;
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}
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if (!strcmp(phymode, "rgmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
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return 0;
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}
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if (!strcmp(phymode, "rmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
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return 0;
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}
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return -EINVAL;
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}
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static int socfpga_eth_reset(void)
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{
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const void *fdt = gd->fdt_blob;
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struct fdtdec_phandle_args args;
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const char *phy_mode;
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u32 phy_modereg;
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int nodes[2]; /* Max. two GMACs */
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int ret, count;
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int i, node;
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/* Put both GMACs into RESET state. */
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socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
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socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
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count = fdtdec_find_aliases_for_id(fdt, "ethernet",
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COMPAT_ALTERA_SOCFPGA_DWMAC,
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nodes, ARRAY_SIZE(nodes));
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for (i = 0; i < count; i++) {
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node = nodes[i];
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if (node <= 0)
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continue;
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ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
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"#reset-cells", 1, 0,
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&args);
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if (ret || (args.args_count != 1)) {
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debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
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continue;
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}
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phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
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ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
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if (ret) {
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debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
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continue;
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}
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dwmac_deassert_reset(args.args[0], phy_modereg);
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}
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return 0;
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}
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#else
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static int socfpga_eth_reset(void)
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{
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return 0;
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};
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#endif
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static const struct {
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const u16 pn;
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const char *name;
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const char *var;
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} socfpga_fpga_model[] = {
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/* Cyclone V E */
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{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
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{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
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{ 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
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{ 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
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{ 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
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/* Cyclone V GX/GT */
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{ 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
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{ 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
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{ 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
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{ 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
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{ 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
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/* Cyclone V SE/SX/ST */
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{ 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
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{ 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
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{ 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
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{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
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/* Arria V */
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{ 0x2d03, "Arria V, D5", "av_d5" },
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};
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static int socfpga_fpga_id(const bool print_id)
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{
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const u32 altera_mi = 0x6e;
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const u32 id = scan_mgr_get_fpga_id();
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const u32 lsb = id & 0x00000001;
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const u32 mi = (id >> 1) & 0x000007ff;
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const u32 pn = (id >> 12) & 0x0000ffff;
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const u32 version = (id >> 28) & 0x0000000f;
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int i;
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if ((mi != altera_mi) || (lsb != 1)) {
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printf("FPGA: Not Altera chip ID\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
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if (pn == socfpga_fpga_model[i].pn)
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break;
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if (i == ARRAY_SIZE(socfpga_fpga_model)) {
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printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
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return -EINVAL;
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}
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if (print_id)
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printf("FPGA: Altera %s, version 0x%01x\n",
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socfpga_fpga_model[i].name, version);
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return i;
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}
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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const u32 bsel =
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SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
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puts("CPU: Altera SoCFPGA Platform\n");
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socfpga_fpga_id(1);
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printf("BOOT: %s\n", bsel_str[bsel].name);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
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const int fpga_id = socfpga_fpga_id(0);
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env_set("bootmode", bsel_str[bsel].mode);
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if (fpga_id >= 0)
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env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
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return socfpga_eth_reset();
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}
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#endif
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/*
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* Convert all NIC-301 AMBA slaves from secure to non-secure
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*/
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static void socfpga_nic301_slave_ns(void)
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{
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writel(0x1, &nic301_regs->lwhps2fpgaregs);
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writel(0x1, &nic301_regs->hps2fpgaregs);
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writel(0x1, &nic301_regs->acp);
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writel(0x1, &nic301_regs->rom);
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writel(0x1, &nic301_regs->ocram);
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writel(0x1, &nic301_regs->sdrdata);
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}
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static u32 iswgrp_handoff[8];
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int arch_early_init_r(void)
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{
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int i;
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/*
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* Write magic value into magic register to unlock support for
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* issuing warm reset. The ancient kernel code expects this
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* value to be written into the register by the bootloader, so
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* to support that old code, we write it here instead of in the
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* reset_cpu() function just before resetting the CPU.
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*/
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writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
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for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
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iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
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socfpga_bridges_reset(1);
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socfpga_nic301_slave_ns();
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/*
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* Private components security:
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* U-Boot : configure private timer, global timer and cpu component
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* access as non secure for kernel stage (as required by Linux)
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*/
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setbits_le32(&scu_regs->sacr, 0xfff);
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/* Configure the L2 controller to make SDRAM start at 0 */
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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writel(0x2, &nic301_regs->remap);
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#else
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writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
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writel(0x1, &pl310->pl310_addr_filter_start);
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#endif
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/* Add device descriptor to FPGA device table */
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socfpga_fpga_add();
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#ifdef CONFIG_DESIGNWARE_SPI
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/* Get Designware SPI controller out of reset */
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socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
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socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
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#endif
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#ifdef CONFIG_NAND_DENALI
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socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
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#endif
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static struct socfpga_reset_manager *reset_manager_base =
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(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
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static struct socfpga_sdr_ctrl *sdr_ctrl =
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(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
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static void socfpga_sdram_apply_static_cfg(void)
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{
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const u32 applymask = 0x8;
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u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
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/*
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* SDRAM staticcfg register specific:
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* When applying the register setting, the CPU must not access
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* SDRAM. Luckily for us, we can abuse i-cache here to help us
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* circumvent the SDRAM access issue. The idea is to make sure
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* that the code is in one full i-cache line by branching past
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* it and back. Once it is in the i-cache, we execute the core
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* of the code and apply the register settings.
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*
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* The code below uses 7 instructions, while the Cortex-A9 has
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* 32-byte cachelines, thus the limit is 8 instructions total.
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*/
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asm volatile(
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".align 5 \n"
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" b 2f \n"
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"1: str %0, [%1] \n"
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" dsb \n"
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" isb \n"
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" b 3f \n"
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"2: b 1b \n"
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"3: nop \n"
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: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
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}
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static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc != 2)
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return CMD_RET_USAGE;
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argv++;
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switch (*argv[0]) {
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case 'e': /* Enable */
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writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
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socfpga_sdram_apply_static_cfg();
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writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
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writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
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writel(iswgrp_handoff[1], &nic301_regs->remap);
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break;
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case 'd': /* Disable */
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writel(0, &sysmgr_regs->fpgaintfgrp_module);
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writel(0, &sdr_ctrl->fpgaport_rst);
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socfpga_sdram_apply_static_cfg();
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writel(0, &reset_manager_base->brg_mod_reset);
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writel(1, &nic301_regs->remap);
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break;
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default:
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(
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bridge, 2, 1, do_bridge,
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"SoCFPGA HPS FPGA bridge control",
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"enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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""
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);
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#endif
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