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https://github.com/brain-hackers/u-boot-brain
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ec00b2e3ab
These are useful for modules that need to be held in reset and are enabled for data to be loaded on to them. Typically these are microcontrollers or other processing entities in the system. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
340 lines
9.6 KiB
C
340 lines
9.6 KiB
C
/*
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* Keystone: PSC configuration module
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/psc_defs.h>
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/**
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* psc_delay() - delay for psc
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*
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* Return: 10
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*/
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int psc_delay(void)
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{
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udelay(10);
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return 10;
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}
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/**
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* psc_wait() - Wait for end of transitional state
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* @domain_num: GPSC domain number
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*
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* Polls pstat for the selected domain and waits for transitions to be complete.
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* Since this is boot loader code it is *ASSUMED* that interrupts are disabled
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* and no other core is mucking around with the psc at the same time.
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*
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* Return: 0 when the domain is free. Returns -1 if a timeout occurred waiting
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* for the completion.
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*/
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int psc_wait(u32 domain_num)
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{
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u32 retry;
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u32 ptstat;
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/*
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* Do nothing if the power domain is in transition. This should never
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* happen since the boot code is the only software accesses psc.
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* It's still remotely possible that the hardware state machines
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* initiate transitions.
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* Don't trap if the domain (or a module in this domain) is
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* stuck in transition.
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*/
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retry = 0;
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do {
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ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT);
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ptstat = ptstat & (1 << domain_num);
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} while ((ptstat != 0) && ((retry += psc_delay()) <
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PSC_PTSTAT_TIMEOUT_LIMIT));
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if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
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return -1;
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return 0;
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}
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/**
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* psc_get_domain_num() - Get the domain number
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* @mod_num: LPSC module number
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*/
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u32 psc_get_domain_num(u32 mod_num)
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{
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u32 domain_num;
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/* Get the power domain associated with the module number */
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domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
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domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
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return domain_num;
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}
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/**
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* psc_set_state() - powers up/down a module
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* @mod_num: LPSC module number
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* @state: 1 to enable, 0 to disable.
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*
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* Powers up/down the requested module and the associated power domain if
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* required. No action is taken it the module is already powered up/down.
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* This only controls modules. The domain in which the module resides will
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* be left in the power on state. Multiple modules can exist in a power
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* domain, so powering down the domain based on a single module is not done.
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*
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* Return: 0 on success, -1 if the module can't be powered up, or if there is a
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* timeout waiting for the transition.
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*/
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int psc_set_state(u32 mod_num, u32 state)
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{
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u32 domain_num;
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u32 pdctl;
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u32 mdctl;
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u32 ptcmd;
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u32 reset_iso;
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u32 v;
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/*
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* Get the power domain associated with the module number, and reset
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* isolation functionality
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*/
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v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
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domain_num = PSC_REG_MDCFG_GET_PD(v);
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reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
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/* Wait for the status of the domain/module to be non-transitional */
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if (psc_wait(domain_num) != 0)
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return -1;
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/*
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* Perform configuration even if the current status matches the
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* existing state
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*
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* Set the next state of the power domain to on. It's OK if the domain
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* is always on. This code will not ever power down a domain, so no
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* change is made if the new state is power down.
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*/
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if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
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pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
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pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
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PSC_REG_VAL_PDCTL_NEXT_ON);
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__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
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}
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/* Set the next state for the module to enabled/disabled */
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
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mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Trigger the enable */
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ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
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ptcmd |= (u32)(1<<domain_num);
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__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
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/* Wait on the complete */
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return psc_wait(domain_num);
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}
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/**
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* psc_enable_module() - power up a module
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* @mod_num: LPSC module number
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*
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* Powers up the requested module and the associated power domain
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* if required. No action is taken it the module is already powered up.
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*
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* Return: 0 on success, -1 if the module can't be powered up, or
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* if there is a timeout waiting for the transition.
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*
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*/
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int psc_enable_module(u32 mod_num)
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{
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u32 mdctl;
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/* Set the bit to apply reset */
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
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return 0;
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return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
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}
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/**
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* psc_disable_module() - Power down a module
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* @mod_num: LPSC module number
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*
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* Return: 0 on success, -1 on failure or timeout.
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*/
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int psc_disable_module(u32 mod_num)
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{
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u32 mdctl;
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/* Set the bit to apply reset */
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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if ((mdctl & 0x3f) == 0)
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return 0;
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mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
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}
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/**
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* psc_set_reset_iso() - Set the reset isolation bit in mdctl
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* @mod_num: LPSC module number
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*
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* The reset isolation enable bit is set. The state of the module is not
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* changed.
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*
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* Return: 0 if the module config showed that reset isolation is supported.
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* Returns 1 otherwise. This is not an error, but setting the bit in mdctl
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* has no effect.
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*/
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int psc_set_reset_iso(u32 mod_num)
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{
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u32 v;
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u32 mdctl;
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/* Set the reset isolation bit */
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
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if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
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return 0;
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return 1;
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}
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/**
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* psc_disable_domain() - Disable a power domain
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* @domain_num: GPSC domain number
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*/
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int psc_disable_domain(u32 domain_num)
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{
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u32 pdctl;
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u32 ptcmd;
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pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
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pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
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pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
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__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
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ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
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ptcmd |= (u32)(1 << domain_num);
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__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
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return psc_wait(domain_num);
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}
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/**
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* psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state
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* @mod_num: LPSC module number
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* @gate_clocks: Can the clocks be gated on this module?
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*
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* Enable the module, but do not release the module from local reset. This is
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* necessary for many processor systems on keystone SoCs to allow for system
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* initialization from a master processor prior to releasing the processor
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* from reset.
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*/
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int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks)
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{
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u32 mdctl, ptcmd, mdstat;
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u32 next_state;
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int domain_num = psc_get_domain_num(mod_num);
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int timeout = 100000;
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/* Wait for any previous transitions to complete */
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psc_wait(domain_num);
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Should be set 0 to assert Local reset */
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if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) {
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mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Wait for transition to take place */
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psc_wait(domain_num);
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}
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/* Clear Module reset */
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF :
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PSC_REG_VAL_MDCTL_NEXT_ON;
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mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Trigger PD transition */
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ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
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ptcmd |= (u32)(1 << domain_num);
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__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
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psc_wait(domain_num);
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mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
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while (timeout) {
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mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
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if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
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PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
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PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
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break;
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timeout--;
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}
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if (!timeout) {
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printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
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__func__, mdstat);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* psc_module_release_from_reset() - Release the module from reset
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* @mod_num: LPSC module number
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*
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* This is the follow through for the command 'psc_module_keep_in_reset_enabled'
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* Allowing the module to be released from reset once all required inits are
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* complete for the module. Typically, this allows the processor module to start
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* execution.
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*/
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int psc_module_release_from_reset(u32 mod_num)
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{
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u32 mdctl, mdstat;
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int domain_num = psc_get_domain_num(mod_num);
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int timeout = 100000;
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/* Wait for any previous transitions to complete */
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psc_wait(domain_num);
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mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Should be set to 1 to de-assert Local reset */
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if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) {
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mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1);
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__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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/* Wait for transition to take place */
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psc_wait(domain_num);
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}
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mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
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while (timeout) {
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mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
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if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
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PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
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PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
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break;
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timeout--;
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}
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if (!timeout) {
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printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
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__func__, mdstat);
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return -ETIMEDOUT;
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}
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return 0;
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}
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