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44a3a91cb0
Do not setup ram start/size in board file. Read it from DT instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* CAUTION: This file is a faked configuration !!!
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* There is no real target for the microblaze-generic
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* configuration. You have to replace this file with
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* the generated file from your Xilinx design flow.
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*/
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#define XILINX_BOARD_NAME microblaze-generic
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 100000000
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/* Microblaze is microblaze_0 */
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#define XILINX_USE_MSR_INSTR 1
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#define XILINX_FSL_NUMBER 3
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/* Interrupt controller is opb_intc_0 */
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#define XILINX_INTC_BASEADDR 0x41200000
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#define XILINX_INTC_NUM_INTR_INPUTS 6
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/* Timer pheriphery is opb_timer_1 */
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#define XILINX_TIMER_BASEADDR 0x41c00000
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#define XILINX_TIMER_IRQ 0
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/* GPIO is LEDs_4Bit*/
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#define XILINX_GPIO_BASEADDR 0x40000000
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/* Flash Memory is FLASH_2Mx32 */
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#define XILINX_FLASH_START 0x2c000000
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#define XILINX_FLASH_SIZE 0x00800000
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/* Watchdog IP is wxi_timebase_wdt_0 */
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#define XILINX_WATCHDOG_BASEADDR 0x50000000
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#define XILINX_WATCHDOG_IRQ 1
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