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https://github.com/brain-hackers/u-boot-brain
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ae6b03fefc
The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __P3060QDS_QIXIS_H__
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#define __P3060QDS_QIXIS_H__
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/* Definitions of QIXIS Registers for P3060QDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EC_MODE_MASK 0x0F
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#define BRDCFG4_EC2_MII_EC1_MII 0x00
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#define BRDCFG4_EC2_MII_EC1_USB 0x03
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#define BRDCFG4_EC2_USB_EC1_MII 0x0C
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#define BRDCFG4_EC2_USB_EC1_USB 0x0F
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#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E
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#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B
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#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A
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#define BRDCFG4_EMISEL_MASK 0xF0
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#define BRDCFG5_ECLKS_MASK 0x80
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#define BRDCFG5_USB1ID_MASK 0x40
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#define BRDCFG5_USB2ID_MASK 0x20
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#define BRDCFG5_GC2MX_MASK 0x0C
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#define BRDCFG5_T15MX_MASK 0x03
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#define BRDCFG5_ECLKS_IEEE1588_CM 0x80
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#define BRDCFG5_USB1ID_CTRL 0x40
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#define BRDCFG5_USB2ID_CTRL 0x20
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#define BRDCFG6_SD1MX_A 0x01
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#define BRDCFG6_SD1MX_B 0x00
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#define BRDCFG6_SD2MX_A 0x02
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#define BRDCFG6_SD2MX_B 0x00
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#define BRDCFG6_SD3MX_A 0x04
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#define BRDCFG6_SD3MX_B 0x00
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#define BRDCFG6_SD4MX_A 0x08
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#define BRDCFG6_SD4MX_B 0x00
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#define BRDCFG7_JTAGMX_MASK 0xC0
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#define BRDCFG7_IQ1MX_MASK 0x20
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#define BRDCFG7_G1MX_MASK 0x10
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#define BRDCFG7_D1MX_MASK 0x0C
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#define BRDCFG7_I3MX_MASK 0x03
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#define BRDCFG7_JTAGMX_AURORA 0x00
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#define BRDCFG7_JTAGMX_FPGA 0x80
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#define BRDCFG7_JTAGMX_COP_JTAG 0xC0
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#define BRDCFG7_IQ1MX_IRQ_EVT 0x00
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#define BRDCFG7_IQ1MX_USB2 0x20
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#define BRDCFG7_G1MX_USB1 0x00
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#define BRDCFG7_G1MX_TSEC3 0x10
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#define BRDCFG7_D1MX_DMA 0x00
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#define BRDCFG7_D1MX_TSEC3USB 0x04
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#define BRDCFG7_D1MX_HDLC2 0x08
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#define BRDCFG7_I3MX_UART2_I2C34 0x00
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#define BRDCFG7_I3MX_GPIO_EVT 0x01
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#define BRDCFG7_I3MX_USB1 0x02
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#define BRDCFG7_I3MX_TSEC3 0x03
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#endif
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