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https://github.com/brain-hackers/u-boot-brain
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7c619ddcee
This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch). Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Freescale non-CPM SPI Controller
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*
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* Copyright 2008 Qstreams Networks, Inc.
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_MPC8XXX_SPI_H_
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#define _ASM_MPC8XXX_SPI_H_
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#include <asm/types.h>
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#if defined(CONFIG_MPC8308) || \
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defined(CONFIG_MPC8313) || \
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defined(CONFIG_MPC8315) || \
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defined(CONFIG_MPC834x) || \
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defined(CONFIG_MPC837x)
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typedef struct spi8xxx {
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u8 res0[0x20]; /* 0x0-0x01f reserved */
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u32 mode; /* mode register */
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u32 event; /* event register */
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u32 mask; /* mask register */
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u32 com; /* command register */
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u32 tx; /* transmit register */
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u32 rx; /* receive register */
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u8 res1[0xFC8]; /* fill up to 0x1000 */
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} spi8xxx_t;
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#endif
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#endif /* _ASM_MPC8XXX_SPI_H_ */
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