mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-18 18:53:22 +09:00
f76eba38b3
This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
68 lines
2.3 KiB
C
68 lines
2.3 KiB
C
/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_NAND_H
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#define _SUNXI_NAND_H
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#include <linux/types.h>
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struct sunxi_nand
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{
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u32 ctl; /* 0x000 Configure and control */
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u32 st; /* 0x004 Status information */
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u32 intr; /* 0x008 Interrupt control */
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u32 timing_ctl; /* 0x00C Timing control */
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u32 timing_cfg; /* 0x010 Timing configure */
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u32 addr_low; /* 0x014 Low word address */
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u32 addr_high; /* 0x018 High word address */
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u32 block_num; /* 0x01C Data block number */
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u32 data_cnt; /* 0x020 Data counter for transfer */
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u32 cmd; /* 0x024 NDFC commands */
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u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
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u32 wcmd_set; /* 0x02C Write command set */
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u32 io_data; /* 0x030 IO data */
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u32 ecc_ctl; /* 0x034 ECC configure and control */
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u32 ecc_st; /* 0x038 ECC status and operation info */
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u32 efr; /* 0x03C Enhanced feature */
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u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
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u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
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u32 user_data[16]; /* 0x050[16] User data field */
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u32 efnand_st; /* 0x090 EFNAND status */
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u32 res0[3];
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u32 spare_area; /* 0x0A0 Spare area configure */
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u32 pat_id; /* 0x0A4 Pattern ID register */
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u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
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u32 rdata_sta_0; /* 0x0AC Read data status 0 */
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u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
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u32 res1[3];
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u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
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u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
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};
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#define SUNXI_NAND_CTL_EN (1 << 0)
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#define SUNXI_NAND_CTL_RST (1 << 1)
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#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
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#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
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#define SUNXI_NAND_ST_CMD_INT (1 << 1)
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#define SUNXI_NAND_ST_DMA_INT (1 << 2)
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#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
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#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
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#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
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#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
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#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
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#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
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#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
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#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
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#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
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#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
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#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
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#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
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#endif /* _SUNXI_NAND_H */
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