John Keeping 2b51784aef rockchip: rk3288: Fix pinctrl for GPIO bank 0 ... Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>		2016-07-31 07:24:20 -06:00
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ath79	drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros qca953x.	2016-05-21 01:25:50 +02:00
exynos	pinctrl: Add pinctrl driver support for Exynos7420 SoC	2016-05-25 10:00:18 +09:00
nxp	pinctrl: imx: Support i.MX7D	2016-02-21 11:25:29 +01:00
rockchip	rockchip: rk3288: Fix pinctrl for GPIO bank 0	2016-07-31 07:24:20 -06:00
uniphier	ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()	2016-07-24 00:13:10 +09:00
Kconfig	cosmetic: rockchip: sort socs according to numbers	2016-07-25 20:44:20 -06:00
Makefile	pinctrl: Add pinctrl driver support for Exynos7420 SoC	2016-05-25 10:00:18 +09:00
pinctrl_pic32.c	dm: Use dm_scan_fdt_dev() directly where possible	2016-07-27 14:15:54 -06:00
pinctrl-generic.c	pinctrl: add pin control uclass support	2015-08-31 07:57:29 -06:00
pinctrl-sandbox.c	pinctrl: sandbox: add sandbox pinctrl driver	2015-08-31 07:57:29 -06:00
pinctrl-uclass.c	pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices	2016-05-25 10:00:18 +09:00