mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
210 lines
4.2 KiB
ArmAsm
210 lines
4.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Renesas Electronics Europe Ltd.
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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*
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* Based on board/renesas/rsk7203/lowlevel_init.S
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* Cache setting */
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write32 CCR1_A ,CCR1_D
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/* io_set_cpg */
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write8 STBCR3_A, STBCR3_D
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write8 STBCR4_A, STBCR4_D
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write8 STBCR5_A, STBCR5_D
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write8 STBCR6_A, STBCR6_D
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write8 STBCR7_A, STBCR7_D
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write8 STBCR8_A, STBCR8_D
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/* ConfigurePortPins */
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/* Leaving LED1 ON for sanity test */
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write16 PJCR1_A, PJCR1_D1
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write16 PJCR2_A, PJCR2_D
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write16 PJIOR0_A, PJIOR0_D1
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write16 PJDR0_A, PJDR0_D
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write16 PJPR0_A, PJPR0_D
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/* Configure EN_PIN & RS_PIN */
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write16 PGCR2_A, PGCR2_D
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write16 PGIOR0_A, PGIOR0_D
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/* Configure the port pins connected to UART */
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write16 PJCR1_A, PJCR1_D2
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write16 PJIOR0_A, PJIOR0_D2
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/* Configure Operating Frequency */
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write16 WTCSR_A, WTCSR_D0
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write16 WTCSR_A, WTCSR_D1
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write16 WTCNT_A, WTCNT_D
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/* Control of RESBANK */
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write16 IBNR_A, IBNR_D
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/* Enable SCIF3 module */
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write16 STBCR4_A, STBCR4_D
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/* Set clock mode*/
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write16 FRQCR_A, FRQCR_D
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/* Configure Bus And Memory */
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init_bsc_cs0:
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pfc_settings:
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write16 PCCR2_A, PCCR2_D
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write16 PCCR1_A, PCCR1_D
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write16 PCCR0_A, PCCR0_D
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write16 PBCR0_A, PBCR0_D
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write16 PBCR1_A, PBCR1_D
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write16 PBCR2_A, PBCR2_D
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write16 PBCR3_A, PBCR3_D
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write16 PBCR4_A, PBCR4_D
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write16 PBCR5_A, PBCR5_D
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write16 PDCR0_A, PDCR0_D
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write16 PDCR1_A, PDCR1_D
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write16 PDCR2_A, PDCR2_D
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write16 PDCR3_A, PDCR3_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS0BCR_A, CS0BCR_D
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init_bsc_cs2:
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write16 PJCR0_A, PJCR0_D
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write32 CS2WCR_A, CS2WCR_D
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init_sdram:
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write32 CS3BCR_A, CS3BCR_D
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write32 CS3WCR_A, CS3WCR_D
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write32 SDCR_A, SDCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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/* wait 200us */
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mov.l REPEAT_D, r3
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mov #0, r2
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repeat0:
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add #1, r2
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cmp/hs r3, r2
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bf repeat0
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nop
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mov.l SDRAM_MODE, r1
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mov #0, r0
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mov.l r0, @r1
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nop
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rts
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.align 4
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CCR1_A: .long CCR1
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CCR1_D: .long 0x0000090B
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FRQCR_A: .long 0xFFFE0010
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FRQCR_D: .word 0x1003
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.align 2
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STBCR3_A: .long 0xFFFE0408
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STBCR3_D: .long 0x00000002
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STBCR4_A: .long 0xFFFE040C
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STBCR4_D: .word 0x0000
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.align 2
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STBCR5_A: .long 0xFFFE0410
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STBCR5_D: .long 0x00000010
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STBCR6_A: .long 0xFFFE0414
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STBCR6_D: .long 0x00000002
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STBCR7_A: .long 0xFFFE0418
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STBCR7_D: .long 0x0000002A
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STBCR8_A: .long 0xFFFE041C
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STBCR8_D: .long 0x0000007E
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PJCR1_A: .long 0xFFFE390C
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PJCR1_D1: .word 0x0000
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PJCR1_D2: .word 0x0022
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PJCR2_A: .long 0xFFFE390A
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PJCR2_D: .word 0x0000
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.align 2
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PJIOR0_A: .long 0xFFFE3912
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PJIOR0_D1: .word 0x0FC0
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PJIOR0_D2: .word 0x0FE0
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PJDR0_A: .long 0xFFFE3916
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PJDR0_D: .word 0x0FBF
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.align 2
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PJPR0_A: .long 0xFFFE391A
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PJPR0_D: .long 0x00000FBF
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PGCR2_A: .long 0xFFFE38CA
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PGCR2_D: .word 0x0000
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.align 2
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PGIOR0_A: .long 0xFFFE38D2
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PGIOR0_D: .word 0x03F0
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.align 2
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WTCSR_A: .long 0xFFFE0000
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WTCSR_D0: .word 0x0000
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WTCSR_D1: .word 0x0000
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WTCNT_A: .long 0xFFFE0002
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WTCNT_D: .word 0x0000
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.align 2
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PCCR0_A: .long 0xFFFE384E
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PDCR0_A: .long 0xFFFE386E
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PDCR1_A: .long 0xFFFE386C
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PDCR2_A: .long 0xFFFE386A
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PDCR3_A: .long 0xFFFE3868
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PBCR0_A: .long 0xFFFE382E
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PBCR1_A: .long 0xFFFE382C
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PBCR2_A: .long 0xFFFE382A
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PBCR3_A: .long 0xFFFE3828
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PBCR4_A: .long 0xFFFE3826
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PBCR5_A: .long 0xFFFE3824
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PCCR0_D: .word 0x1111
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PDCR0_D: .word 0x1111
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PDCR1_D: .word 0x1111
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PDCR2_D: .word 0x1111
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PDCR3_D: .word 0x1111
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PBCR0_D: .word 0x1110
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PBCR1_D: .word 0x1111
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PBCR2_D: .word 0x1111
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PBCR3_D: .word 0x1111
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PBCR4_D: .word 0x1111
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PBCR5_D: .word 0x0111
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.align 2
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CS0WCR_A: .long 0xFFFC0028
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CS0WCR_D: .long 0x00000B41
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CS0BCR_A: .long 0xFFFC0004
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CS0BCR_D: .long 0x10000400
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PJCR0_A: .long 0xFFFE390E
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PJCR0_D: .word 0x3300
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.align 2
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CS2WCR_A: .long 0xFFFC0030
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CS2WCR_D: .long 0x00000B01
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PCCR2_A: .long 0xFFFE384A
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PCCR2_D: .word 0x0001
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.align 2
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PCCR1_A: .long 0xFFFE384C
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PCCR1_D: .word 0x1111
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.align 2
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CS3BCR_A: .long 0xFFFC0010
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CS3BCR_D: .long 0x00004400
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CS3WCR_A: .long 0xFFFC0034
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CS3WCR_D: .long 0x0000288A
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SDCR_A: .long 0xFFFC004C
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SDCR_D: .long 0x00000812
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RTCOR_A: .long 0xFFFC0058
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RTCOR_D: .long 0xA55A0046
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RTCSR_A: .long 0xFFFC0050
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RTCSR_D: .long 0xA55A0010
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IBNR_A: .long 0xFFFE080E
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IBNR_D: .word 0x0000
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.align 2
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SDRAM_MODE: .long 0xFFFC5040
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REPEAT_D: .long 0x00000085
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