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https://github.com/brain-hackers/u-boot-brain
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cf97b2213a
When referring to the MSTPSR register, it contains the clock status of SYS, RT, SECURE, and controlling SMSTPCR using this value has the problem of being affected by the RT and SECURE status.This patch changes the reference register to SMSTPCR. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
109 lines
2.4 KiB
C
109 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/draak/draak.c
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* This file is Draak board support.
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void)
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{
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
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#define DVFS_MSTP926 BIT(26)
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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int board_early_init_f(void)
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{
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
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#endif
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return 0;
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}
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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/* USB1 pull-up */
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
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/* Configure the HSUSB block */
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mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
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/* Choice USB0SEL */
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clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
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HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_RSTOUTCR (RST_BASE + 0x58)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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void reset_cpu(ulong addr)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else if (cputype == 0xd07)
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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else
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hang();
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}
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