mirror of
https://github.com/brain-hackers/u-boot-brain
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6f41d1a17e
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio". Use compatible string used by kernel instead and identify mmci variant using "arm,primecell-periphid" property. Currently, the DM part of mmci driver is only used by STM32 SoCs, that's why the switch case gets only one entry. It will be populated easily with new variant in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
200 lines
5.9 KiB
C
200 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ARM PrimeCell MultiMedia Card Interface - PL180
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*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Ulf Hansson <ulf.hansson@stericsson.com>
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* Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
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* Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
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*/
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#ifndef __ARM_PL180_MMCI_H__
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#define __ARM_PL180_MMCI_H__
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/* need definition of struct mmc_config */
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#include <mmc.h>
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#define COMMAND_REG_DELAY 300
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#define DATA_REG_DELAY 1000
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#define CLK_CHANGE_DELAY 2000
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#define INIT_PWR 0xBF /* Power on, full power, not open drain */
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#define ARM_MCLK (100*1000*1000)
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/* SDI Power Control register bits */
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#define SDI_PWR_PWRCTRL_MASK 0x00000003
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#define SDI_PWR_PWRCTRL_ON 0x00000003
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#define SDI_PWR_PWRCTRL_OFF 0x00000000
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#define SDI_PWR_DAT2DIREN 0x00000004
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#define SDI_PWR_CMDDIREN 0x00000008
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#define SDI_PWR_DAT0DIREN 0x00000010
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#define SDI_PWR_DAT31DIREN 0x00000020
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#define SDI_PWR_OPD 0x00000040
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#define SDI_PWR_FBCLKEN 0x00000080
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#define SDI_PWR_DAT74DIREN 0x00000100
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#define SDI_PWR_RSTEN 0x00000200
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#define VOLTAGE_WINDOW_MMC 0x00FF8080
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#define VOLTAGE_WINDOW_SD 0x80010000
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/* SDI clock control register bits */
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#define SDI_CLKCR_CLKDIV_MASK 0x000000FF
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#define SDI_CLKCR_CLKEN 0x00000100
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#define SDI_CLKCR_PWRSAV 0x00000200
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#define SDI_CLKCR_BYPASS 0x00000400
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#define SDI_CLKCR_WIDBUS_MASK 0x00001800
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#define SDI_CLKCR_WIDBUS_1 0x00000000
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#define SDI_CLKCR_WIDBUS_4 0x00000800
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/* V2 only */
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#define SDI_CLKCR_WIDBUS_8 0x00001000
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#define SDI_CLKCR_NEDGE 0x00002000
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#define SDI_CLKCR_HWFC_EN 0x00004000
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#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
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#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
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/* SDI command register bits */
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#define SDI_CMD_CMDINDEX_MASK 0x000000FF
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#define SDI_CMD_WAITRESP 0x00000040
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#define SDI_CMD_LONGRESP 0x00000080
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#define SDI_CMD_WAITINT 0x00000100
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#define SDI_CMD_WAITPEND 0x00000200
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#define SDI_CMD_CPSMEN 0x00000400
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#define SDI_CMD_SDIOSUSPEND 0x00000800
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#define SDI_CMD_ENDCMDCOMPL 0x00001000
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#define SDI_CMD_NIEN 0x00002000
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#define SDI_CMD_CE_ATACMD 0x00004000
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#define SDI_CMD_CBOOTMODEEN 0x00008000
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#define SDI_DTIMER_DEFAULT 0xFFFF0000
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/* SDI Status register bits */
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#define SDI_STA_CCRCFAIL 0x00000001
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#define SDI_STA_DCRCFAIL 0x00000002
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#define SDI_STA_CTIMEOUT 0x00000004
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#define SDI_STA_DTIMEOUT 0x00000008
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#define SDI_STA_TXUNDERR 0x00000010
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#define SDI_STA_RXOVERR 0x00000020
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#define SDI_STA_CMDREND 0x00000040
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#define SDI_STA_CMDSENT 0x00000080
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#define SDI_STA_DATAEND 0x00000100
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#define SDI_STA_STBITERR 0x00000200
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#define SDI_STA_DBCKEND 0x00000400
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#define SDI_STA_CMDACT 0x00000800
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#define SDI_STA_TXACT 0x00001000
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#define SDI_STA_RXACT 0x00002000
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#define SDI_STA_TXFIFOBW 0x00004000
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#define SDI_STA_RXFIFOBR 0x00008000
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#define SDI_STA_TXFIFOF 0x00010000
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#define SDI_STA_RXFIFOF 0x00020000
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#define SDI_STA_TXFIFOE 0x00040000
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#define SDI_STA_RXFIFOE 0x00080000
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#define SDI_STA_TXDAVL 0x00100000
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#define SDI_STA_RXDAVL 0x00200000
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#define SDI_STA_SDIOIT 0x00400000
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#define SDI_STA_CEATAEND 0x00800000
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#define SDI_STA_CARDBUSY 0x01000000
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#define SDI_STA_BOOTMODE 0x02000000
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#define SDI_STA_BOOTACKERR 0x04000000
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#define SDI_STA_BOOTACKTIMEOUT 0x08000000
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#define SDI_STA_RSTNEND 0x10000000
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/* SDI Interrupt Clear register bits */
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#define SDI_ICR_MASK 0x1DC007FF
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#define SDI_ICR_CCRCFAILC 0x00000001
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#define SDI_ICR_DCRCFAILC 0x00000002
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#define SDI_ICR_CTIMEOUTC 0x00000004
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#define SDI_ICR_DTIMEOUTC 0x00000008
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#define SDI_ICR_TXUNDERRC 0x00000010
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#define SDI_ICR_RXOVERRC 0x00000020
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#define SDI_ICR_CMDRENDC 0x00000040
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#define SDI_ICR_CMDSENTC 0x00000080
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#define SDI_ICR_DATAENDC 0x00000100
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#define SDI_ICR_STBITERRC 0x00000200
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#define SDI_ICR_DBCKENDC 0x00000400
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#define SDI_ICR_SDIOITC 0x00400000
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#define SDI_ICR_CEATAENDC 0x00800000
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#define SDI_ICR_BUSYENDC 0x01000000
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#define SDI_ICR_BOOTACKERRC 0x04000000
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#define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
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#define SDI_ICR_RSTNENDC 0x10000000
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#define SDI_MASK0_MASK 0x1FFFFFFF
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/* SDI Data control register bits */
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#define SDI_DCTRL_DTEN 0x00000001
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#define SDI_DCTRL_DTDIR_IN 0x00000002
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#define SDI_DCTRL_DTMODE_STREAM 0x00000004
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#define SDI_DCTRL_DMAEN 0x00000008
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#define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
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#define SDI_DCTRL_RWSTART 0x00000100
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#define SDI_DCTRL_RWSTOP 0x00000200
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#define SDI_DCTRL_RWMOD 0x00000200
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#define SDI_DCTRL_SDIOEN 0x00000800
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#define SDI_DCTRL_DMAREQCTL 0x00001000
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#define SDI_DCTRL_DBOOTMODEEN 0x00002000
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#define SDI_DCTRL_BUSYMODE 0x00004000
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#define SDI_DCTRL_DDR_MODE 0x00008000
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#define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000
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#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16
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#define SDI_FIFO_BURST_SIZE 8
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#define STM32_MMCI_ID 0x00880180
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struct sdi_registers {
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u32 power; /* 0x00*/
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u32 clock; /* 0x04*/
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u32 argument; /* 0x08*/
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u32 command; /* 0x0c*/
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u32 respcommand; /* 0x10*/
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u32 response0; /* 0x14*/
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u32 response1; /* 0x18*/
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u32 response2; /* 0x1c*/
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u32 response3; /* 0x20*/
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u32 datatimer; /* 0x24*/
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u32 datalength; /* 0x28*/
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u32 datactrl; /* 0x2c*/
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u32 datacount; /* 0x30*/
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u32 status; /* 0x34*/
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u32 status_clear; /* 0x38*/
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u32 mask0; /* 0x3c*/
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u32 mask1; /* 0x40*/
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u32 card_select; /* 0x44*/
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u32 fifo_count; /* 0x48*/
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u32 padding1[(0x80-0x4C)>>2];
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u32 fifo; /* 0x80*/
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u32 padding2[(0xFE0-0x84)>>2];
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u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
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u32 periph_id1; /* 0xFE4*/
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u32 periph_id2; /* 0xFE8*/
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u32 periph_id3; /* 0xFEC*/
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u32 pcell_id0; /* 0xFF0*/
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u32 pcell_id1; /* 0xFF4*/
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u32 pcell_id2; /* 0xFF8*/
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u32 pcell_id3; /* 0xFFC*/
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};
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struct pl180_mmc_host {
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struct sdi_registers *base;
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char name[32];
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unsigned int b_max;
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unsigned int voltages;
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unsigned int caps;
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unsigned int clock_in;
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unsigned int clock_min;
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unsigned int clock_max;
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unsigned int clkdiv_init;
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unsigned int pwr_init;
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int version2;
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struct mmc_config cfg;
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#ifdef CONFIG_DM_MMC
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struct gpio_desc cd_gpio;
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#endif
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};
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int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc);
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#endif
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