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![Simon Glass](/assets/img/avatar_default.png)
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
230 lines
4.9 KiB
C
230 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <spi.h>
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#include <dm.h>
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#include <div64.h>
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#include <errno.h>
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#include <time.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <dm/pinctrl.h>
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#include <mach/ar71xx_regs.h>
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/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
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#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
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#define ATH79_SPI_RRW_DELAY_FACTOR 12000
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#define ATH79_SPI_MHZ (1000 * 1000)
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struct ath79_spi_priv {
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void __iomem *regs;
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u32 rrw_delay;
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};
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct ath79_spi_priv *priv = dev_get_priv(bus);
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writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
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writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
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}
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct ath79_spi_priv *priv = dev_get_priv(bus);
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writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
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writel(0, priv->regs + AR71XX_SPI_REG_FS);
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}
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static int ath79_spi_claim_bus(struct udevice *dev)
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{
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return 0;
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}
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static int ath79_spi_release_bus(struct udevice *dev)
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{
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return 0;
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}
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static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct ath79_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
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u8 *rx = din;
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const u8 *tx = dout;
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u8 curbyte, curbitlen, restbits;
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u32 bytes = bitlen / 8;
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u32 out, in;
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u64 tick;
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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restbits = (bitlen % 8);
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if (restbits)
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bytes++;
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out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
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while (bytes > 0) {
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bytes--;
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curbyte = 0;
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if (tx)
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curbyte = *tx++;
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if (restbits && !bytes) {
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curbitlen = restbits;
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curbyte <<= 8 - restbits;
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} else {
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curbitlen = 8;
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}
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for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
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if (curbyte & 0x80)
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out |= AR71XX_SPI_IOC_DO;
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else
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out &= ~(AR71XX_SPI_IOC_DO);
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writel(out, priv->regs + AR71XX_SPI_REG_IOC);
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/* delay for low level */
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if (priv->rrw_delay) {
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tick = get_ticks() + priv->rrw_delay;
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while (get_ticks() < tick)
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/*NOP*/;
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}
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writel(out | AR71XX_SPI_IOC_CLK,
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priv->regs + AR71XX_SPI_REG_IOC);
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/* delay for high level */
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if (priv->rrw_delay) {
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tick = get_ticks() + priv->rrw_delay;
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while (get_ticks() < tick)
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/*NOP*/;
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}
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curbyte <<= 1;
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}
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if (!bytes)
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writel(out, priv->regs + AR71XX_SPI_REG_IOC);
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in = readl(priv->regs + AR71XX_SPI_REG_RDS);
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if (rx) {
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if (restbits && !bytes)
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*rx++ = (in << (8 - restbits));
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else
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*rx++ = in;
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}
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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return 0;
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}
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static int ath79_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct ath79_spi_priv *priv = dev_get_priv(bus);
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u32 val, div = 0;
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u64 time;
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if (speed)
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div = get_bus_freq(0) / speed;
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if (div > 63)
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div = 63;
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if (div < 5)
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div = 5;
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/* calculate delay */
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time = get_tbclk();
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do_div(time, speed / 2);
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val = get_bus_freq(0) / ATH79_SPI_MHZ;
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val = ATH79_SPI_RRW_DELAY_FACTOR / val;
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if (time > val)
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priv->rrw_delay = time - val + 1;
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else
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priv->rrw_delay = 0;
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writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
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clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
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AR71XX_SPI_CTRL_DIV_MASK,
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ATH79_SPI_CLK_DIV(div));
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writel(0, priv->regs + AR71XX_SPI_REG_FS);
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return 0;
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}
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static int ath79_spi_set_mode(struct udevice *bus, uint mode)
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{
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return 0;
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}
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static int ath79_spi_probe(struct udevice *bus)
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{
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struct ath79_spi_priv *priv = dev_get_priv(bus);
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fdt_addr_t addr;
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addr = devfdt_get_addr(bus);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = map_physmem(addr,
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AR71XX_SPI_SIZE,
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MAP_NOCACHE);
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/* Init SPI Hardware, disable remap, set clock */
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writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
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writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
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priv->regs + AR71XX_SPI_REG_CTRL);
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writel(0, priv->regs + AR71XX_SPI_REG_FS);
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return 0;
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}
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static int ath79_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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/* Always allow activity on CS 0/1/2 */
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if (cs >= 3)
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return -EINVAL;
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return 0;
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}
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static const struct dm_spi_ops ath79_spi_ops = {
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.claim_bus = ath79_spi_claim_bus,
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.release_bus = ath79_spi_release_bus,
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.xfer = ath79_spi_xfer,
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.set_speed = ath79_spi_set_speed,
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.set_mode = ath79_spi_set_mode,
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.cs_info = ath79_cs_info,
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};
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static const struct udevice_id ath79_spi_ids[] = {
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{ .compatible = "qca,ar7100-spi" },
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{}
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};
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U_BOOT_DRIVER(ath79_spi) = {
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.name = "ath79_spi",
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.id = UCLASS_SPI,
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.of_match = ath79_spi_ids,
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.ops = &ath79_spi_ops,
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.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
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.probe = ath79_spi_probe,
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};
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