mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
258 lines
6.4 KiB
C
258 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+159
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/*
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* Take from dc tegra_ahub.c
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*
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* Copyright 2018 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_MISC
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#include <common.h>
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#include <dm.h>
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#include <i2s.h>
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#include <log.h>
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#include <misc.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_ahub.h>
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#include <asm/arch-tegra/tegra_i2s.h>
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#include "tegra_i2s_priv.h"
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struct tegra_ahub_priv {
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struct apbif_regs *apbif_regs;
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struct xbar_regs *xbar_regs;
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u32 full_mask;
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int capacity_words; /* FIFO capacity in words */
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/*
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* This is unset intially, but is set by tegra_ahub_ioctl() called
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* from the misc_ioctl() in tegra_sound_probe()
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*/
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struct udevice *i2s;
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struct udevice *dma;
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};
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static int tegra_ahub_xbar_enable_i2s(struct xbar_regs *regs, int i2s_id)
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{
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/*
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* Enables I2S as the receiver of APBIF by writing APBIF_TX0 (0x01) to
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* the rx0 register
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*/
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switch (i2s_id) {
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case 0:
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writel(1, ®s->i2s0_rx0);
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break;
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case 1:
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writel(1, ®s->i2s1_rx0);
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break;
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case 2:
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writel(1, ®s->i2s2_rx0);
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break;
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case 3:
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writel(1, ®s->i2s3_rx0);
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break;
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case 4:
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writel(1, ®s->i2s4_rx0);
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break;
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default:
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log_err("Invalid I2S component id: %d\n", i2s_id);
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return -EINVAL;
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}
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return 0;
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}
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static int tegra_ahub_apbif_is_full(struct udevice *dev)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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return readl(&priv->apbif_regs->apbdma_live_stat) & priv->full_mask;
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}
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/**
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* tegra_ahub_wait_for_space() - Wait for space in the FIFO
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*
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* @return 0 if OK, -ETIMEDOUT if no space was available in time
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*/
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static int tegra_ahub_wait_for_space(struct udevice *dev)
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{
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int i = 100000;
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ulong start;
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/* Busy-wait initially, since this should take almost no time */
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while (i--) {
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if (!tegra_ahub_apbif_is_full(dev))
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return 0;
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}
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/* Failed, so do a slower loop for 100ms */
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start = get_timer(0);
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while (tegra_ahub_apbif_is_full(dev)) {
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if (get_timer(start) > 100)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int tegra_ahub_apbif_send(struct udevice *dev, int offset,
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const void *buf, int len)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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const u32 *data = (const u32 *)buf;
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ssize_t written = 0;
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if (len % sizeof(*data)) {
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log_err("Data size (%zd) must be aligned to %zd.\n", len,
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sizeof(*data));
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return -EFAULT;
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}
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while (written < len) {
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int ret = tegra_ahub_wait_for_space(dev);
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if (ret)
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return ret;
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writel(*data++, &priv->apbif_regs->channel0_txfifo);
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written += sizeof(*data);
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}
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return written;
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}
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static void tegra_ahub_apbif_set_cif(struct udevice *dev, u32 value)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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writel(value, &priv->apbif_regs->channel0_cif_tx0_ctrl);
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}
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static void tegra_ahub_apbif_enable_channel0(struct udevice *dev,
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int fifo_threshold)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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u32 ctrl = TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN |
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TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 |
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TEGRA_AHUB_CHANNEL_CTRL_TX_EN;
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fifo_threshold--; /* fifo_threshold starts from 1 */
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ctrl |= (fifo_threshold << TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT);
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writel(ctrl, &priv->apbif_regs->channel0_ctrl);
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}
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static u32 tegra_ahub_get_cif(bool is_receive, uint channels,
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uint bits_per_sample, uint fifo_threshold)
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{
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uint audio_bits = (bits_per_sample >> 2) - 1;
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u32 val;
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channels--; /* Channels in CIF starts from 1 */
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fifo_threshold--; /* FIFO threshold starts from 1 */
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/* Assume input and output are always using same channel / bits */
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val = channels << TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT |
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channels << TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT |
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audio_bits << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT |
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audio_bits << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT |
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fifo_threshold << TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT |
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(is_receive ? TEGRA_AUDIOCIF_DIRECTION_RX <<
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TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT : 0);
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return val;
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}
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static int tegra_ahub_enable(struct udevice *dev)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(priv->i2s);
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u32 cif_ctrl = 0;
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int ret;
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/* We use APBIF channel0 as a sender */
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priv->full_mask = TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL;
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priv->capacity_words = 8;
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/*
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* FIFO is inactive until (fifo_threshold) of words are sent. For
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* better performance, we want to set it to half of capacity.
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*/
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u32 fifo_threshold = priv->capacity_words / 2;
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/*
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* Setup audio client interface (ACIF): APBIF (channel0) as sender and
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* I2S as receiver
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*/
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cif_ctrl = tegra_ahub_get_cif(true, uc_priv->channels,
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uc_priv->bitspersample, fifo_threshold);
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tegra_i2s_set_cif_tx_ctrl(priv->i2s, cif_ctrl);
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cif_ctrl = tegra_ahub_get_cif(false, uc_priv->channels,
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uc_priv->bitspersample, fifo_threshold);
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tegra_ahub_apbif_set_cif(dev, cif_ctrl);
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tegra_ahub_apbif_enable_channel0(dev, fifo_threshold);
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ret = tegra_ahub_xbar_enable_i2s(priv->xbar_regs, uc_priv->id);
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if (ret)
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return ret;
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log_debug("ahub: channels=%d, bitspersample=%d, cif_ctrl=%x, fifo_threshold=%d, id=%d\n",
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uc_priv->channels, uc_priv->bitspersample, cif_ctrl,
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fifo_threshold, uc_priv->id);
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return 0;
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}
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static int tegra_ahub_ioctl(struct udevice *dev, unsigned long request,
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void *buf)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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if (request != AHUB_MISCOP_SET_I2S)
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return -ENOSYS;
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priv->i2s = *(struct udevice **)buf;
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log_debug("i2s set to '%s'\n", priv->i2s->name);
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return tegra_ahub_enable(dev);
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}
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static int tegra_ahub_probe(struct udevice *dev)
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{
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struct tegra_ahub_priv *priv = dev_get_priv(dev);
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ulong addr;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE) {
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log_debug("Invalid apbif address\n");
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return -EINVAL;
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}
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priv->apbif_regs = (struct apbif_regs *)addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE) {
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log_debug("Invalid xbar address\n");
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return -EINVAL;
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}
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priv->xbar_regs = (struct xbar_regs *)addr;
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log_debug("ahub apbif_regs=%p, xbar_regs=%p\n", priv->apbif_regs,
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priv->xbar_regs);
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return 0;
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}
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static struct misc_ops tegra_ahub_ops = {
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.write = tegra_ahub_apbif_send,
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.ioctl = tegra_ahub_ioctl,
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};
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static const struct udevice_id tegra_ahub_ids[] = {
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{ .compatible = "nvidia,tegra124-ahub" },
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{ }
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};
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U_BOOT_DRIVER(tegra_ahub) = {
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.name = "tegra_ahub",
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.id = UCLASS_MISC,
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.of_match = tegra_ahub_ids,
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.ops = &tegra_ahub_ops,
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.probe = tegra_ahub_probe,
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.priv_auto_alloc_size = sizeof(struct tegra_ahub_priv),
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};
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