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![Jagan Teki](/assets/img/avatar_default.png)
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
206 lines
4.4 KiB
C
206 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip PCIe PHY driver
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*
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* Copyright (c) 2016 Rockchip, Inc.
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <asm/arch-rockchip/clock.h>
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#include "pcie_rockchip.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
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{
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u32 reg;
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reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
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reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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udelay(1);
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reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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udelay(1);
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reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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}
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static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
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{
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int ret = 0;
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u32 reg, status;
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ret = reset_deassert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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return ret;
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}
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reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll lock timeout!\n");
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goto err_pll_lock;
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}
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phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
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phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
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ret = -ETIMEDOUT;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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!(status & PHY_PLL_OUTPUT),
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll output enable timeout!\n");
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goto err_pll_lock;
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}
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reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll relock timeout!\n");
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goto err_pll_lock;
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}
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return 0;
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err_pll_lock:
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reset_assert(&phy->phy_rst);
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return ret;
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}
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static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
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{
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int ret;
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u32 reg;
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reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
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ret = reset_assert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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return ret;
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}
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return 0;
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}
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static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
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{
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int ret;
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ret = clk_enable(&phy->refclk);
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if (ret) {
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dev_err(dev, "failed to enable refclk clock\n");
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return ret;
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}
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ret = reset_assert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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goto err_reset;
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}
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return 0;
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err_reset:
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clk_disable(&phy->refclk);
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return ret;
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}
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static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
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{
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clk_disable(&phy->refclk);
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return 0;
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}
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static struct rockchip_pcie_phy_ops pcie_phy_ops = {
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.init = rockchip_pcie_phy_init,
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.power_on = rockchip_pcie_phy_power_on,
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.power_off = rockchip_pcie_phy_power_off,
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.exit = rockchip_pcie_phy_exit,
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};
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int rockchip_pcie_phy_get(struct udevice *dev)
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{
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struct rockchip_pcie *priv = dev_get_priv(dev);
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struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
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ofnode phy_node;
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u32 phandle;
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int ret;
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phandle = dev_read_u32_default(dev, "phys", 0);
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phy_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(phy_node)) {
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dev_err(dev, "failed to found pcie-phy\n");
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return -ENODEV;
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}
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phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
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if (ret) {
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dev_err(dev, "failed to get refclk clock phandle\n");
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return ret;
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}
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ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
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if (ret) {
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dev_err(dev, "failed to get phy reset phandle\n");
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return ret;
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}
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phy_priv->ops = &pcie_phy_ops;
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priv->phy = phy_priv;
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return 0;
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}
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