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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
280 lines
7.4 KiB
C
280 lines
7.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs serial gpio driver
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*
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* Author: <lars.povlsen@microchip.com>
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*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <clk.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#define MSCC_SGPIOS_PER_BANK 32
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#define MSCC_SGPIO_BANK_DEPTH 4
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enum {
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REG_INPUT_DATA,
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REG_PORT_CONFIG,
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REG_PORT_ENABLE,
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REG_SIO_CONFIG,
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REG_SIO_CLOCK,
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MAXREG
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};
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struct mscc_sgpio_bf {
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u8 beg;
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u8 end;
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};
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struct mscc_sgpio_props {
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u8 regoff[MAXREG];
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struct mscc_sgpio_bf auto_repeat;
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struct mscc_sgpio_bf port_width;
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struct mscc_sgpio_bf clk_freq;
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struct mscc_sgpio_bf bit_source;
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};
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#define __M(bf) GENMASK((bf).end, (bf).beg)
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#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
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#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
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#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
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#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
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#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
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#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
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#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
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#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
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#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
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const struct mscc_sgpio_props props_luton = {
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.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
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.auto_repeat = { 5, 5 },
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.port_width = { 2, 3 },
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.clk_freq = { 0, 11 },
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.bit_source = { 0, 11 },
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};
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const struct mscc_sgpio_props props_ocelot = {
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.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
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.auto_repeat = { 10, 10 },
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.port_width = { 7, 8 },
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.clk_freq = { 8, 19 },
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.bit_source = { 12, 23 },
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};
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struct mscc_sgpio_priv {
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u32 bitcount;
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u32 ports;
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u32 clock;
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u32 mode[MSCC_SGPIOS_PER_BANK];
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u32 __iomem *regs;
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const struct mscc_sgpio_props *props;
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};
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static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
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{
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u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
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return readl(reg);
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}
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static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
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u32 val, u32 rno, u32 off)
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{
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u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
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writel(val, reg);
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}
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static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
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u32 rno, u32 off, u32 clear, u32 set)
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{
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u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
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clrsetbits_le32(reg, clear, set);
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}
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static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
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{
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struct mscc_sgpio_priv *priv = dev_get_priv(dev);
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u32 port = gpio % MSCC_SGPIOS_PER_BANK;
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u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
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priv->mode[port] |= BIT(bit);
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return 0;
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}
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static int mscc_sgpio_direction_output(struct udevice *dev,
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unsigned int gpio, int value)
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{
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struct mscc_sgpio_priv *priv = dev_get_priv(dev);
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u32 port = gpio % MSCC_SGPIOS_PER_BANK;
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u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
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u32 mask = 3 << (3 * bit);
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debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
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port, bit, mask, value);
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value = (value & 3) << (3 * bit);
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sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
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MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
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MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
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clrbits_le32(&priv->mode[port], BIT(bit));
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return 0;
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}
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static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
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{
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struct mscc_sgpio_priv *priv = dev_get_priv(dev);
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u32 port = gpio % MSCC_SGPIOS_PER_BANK;
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u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
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u32 val = priv->mode[port] & BIT(bit);
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if (val)
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return GPIOF_INPUT;
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else
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return GPIOF_OUTPUT;
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}
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static int mscc_sgpio_set_value(struct udevice *dev,
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unsigned int gpio, int value)
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{
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return mscc_sgpio_direction_output(dev, gpio, value);
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}
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static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
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{
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struct mscc_sgpio_priv *priv = dev_get_priv(dev);
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u32 port = gpio % MSCC_SGPIOS_PER_BANK;
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u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
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int ret;
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if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
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ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
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} else {
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u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
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ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
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ret = !!(ret & (3 << (3 * bit)));
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}
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debug("get: gpio %d, port %d, bit %d, value %d\n",
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gpio, port, bit, ret);
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return ret;
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}
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static int mscc_sgpio_get_count(struct udevice *dev)
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{
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struct ofnode_phandle_args args;
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int count = 0, i = 0, ret;
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ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
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while (ret != -ENOENT) {
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count += args.args[2];
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ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
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++i, &args);
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}
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return count;
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}
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static int mscc_sgpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mscc_sgpio_priv *priv = dev_get_priv(dev);
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int err, div_clock = 0, port;
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u32 val;
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struct clk clk;
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err = clk_get_by_index(dev, 0, &clk);
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if (!err) {
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err = clk_get_rate(&clk);
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if (IS_ERR_VALUE(err)) {
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dev_err(dev, "Invalid clk rate\n");
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return -EINVAL;
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}
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div_clock = err;
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} else {
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dev_err(dev, "Failed to get clock\n");
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return err;
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}
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priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
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priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
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priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
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12500000);
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if (priv->clock <= 0 || priv->clock > div_clock) {
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dev_err(dev, "Invalid frequency %d\n", priv->clock);
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return -EINVAL;
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}
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uc_priv->gpio_count = mscc_sgpio_get_count(dev);
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uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
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uc_priv->gpio_count);
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if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
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(4 * MSCC_SGPIOS_PER_BANK)) {
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dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
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return -EINVAL;
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}
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priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
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MSCC_SGPIOS_PER_BANK);
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debug("probe: gpios = %d, bit-count = %d\n",
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uc_priv->gpio_count, priv->bitcount);
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priv->regs = (u32 __iomem *)dev_read_addr(dev);
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uc_priv->bank_name = "sgpio";
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sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
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MSCC_M_CFG_SIO_PORT_WIDTH(priv),
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MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
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MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
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val = div_clock / priv->clock;
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debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
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div_clock / 1000, priv->clock / 1000, val);
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sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
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MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
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MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
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for (port = 0; port < 32; port++)
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sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
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sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
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debug("probe: sgpio regs = %p\n", priv->regs);
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return 0;
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}
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static const struct dm_gpio_ops mscc_sgpio_ops = {
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.direction_input = mscc_sgpio_direction_input,
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.direction_output = mscc_sgpio_direction_output,
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.get_function = mscc_sgpio_get_function,
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.get_value = mscc_sgpio_get_value,
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.set_value = mscc_sgpio_set_value,
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};
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static const struct udevice_id mscc_sgpio_ids[] = {
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{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
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{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
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{ }
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};
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U_BOOT_DRIVER(gpio_mscc_sgpio) = {
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.name = "mscc-sgpio",
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.id = UCLASS_GPIO,
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.of_match = mscc_sgpio_ids,
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.ops = &mscc_sgpio_ops,
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.probe = mscc_sgpio_probe,
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.priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),
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};
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