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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
193 lines
4.3 KiB
C
193 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Take drivers/gpio/gpio-74x164.c as reference.
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*
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* 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
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*
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* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* struct gen_74x164_chip - Data for 74Hx164
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*
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* @oe: OE pin
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* @nregs: number of registers
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* @buffer: buffer for chained chips
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*/
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#define GEN_74X164_NUMBER_GPIOS 8
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struct gen_74x164_priv {
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struct gpio_desc oe;
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u32 nregs;
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/*
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* Since the nregs are chained, every byte sent will make
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* the previous byte shift to the next register in the
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* chain. Thus, the first byte sent will end up in the last
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* register at the end of the transfer. So, to have a logical
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* numbering, store the bytes in reverse order.
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*/
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u8 *buffer;
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};
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static int gen_74x164_write_conf(struct udevice *dev)
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{
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struct gen_74x164_priv *priv = dev_get_priv(dev);
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int ret;
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ret = dm_spi_claim_bus(dev);
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if (ret)
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return ret;
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ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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dm_spi_release_bus(dev);
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return ret;
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}
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static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
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{
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struct gen_74x164_priv *priv = dev_get_priv(dev);
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uint bank = priv->nregs - 1 - offset / 8;
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uint pin = offset % 8;
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return (priv->buffer[bank] >> pin) & 0x1;
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}
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static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct gen_74x164_priv *priv = dev_get_priv(dev);
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uint bank = priv->nregs - 1 - offset / 8;
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uint pin = offset % 8;
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int ret;
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if (value)
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priv->buffer[bank] |= 1 << pin;
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else
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priv->buffer[bank] &= ~(1 << pin);
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ret = gen_74x164_write_conf(dev);
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if (ret)
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return ret;
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return 0;
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}
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static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
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{
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return -ENOSYS;
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}
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static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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return gen_74x164_set_value(dev, offset, value);
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}
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static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
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{
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return GPIOF_OUTPUT;
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}
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static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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desc->offset = args->args[0];
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops gen_74x164_ops = {
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.direction_input = gen_74x164_direction_input,
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.direction_output = gen_74x164_direction_output,
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.get_value = gen_74x164_get_value,
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.set_value = gen_74x164_set_value,
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.get_function = gen_74x164_get_function,
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.xlate = gen_74x164_xlate,
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};
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static int gen_74x164_probe(struct udevice *dev)
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{
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struct gen_74x164_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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char *str, name[32];
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int ret;
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(dev);
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snprintf(name, sizeof(name), "%s_", dev->name);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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/*
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* See Linux kernel:
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* Documentation/devicetree/bindings/gpio/gpio-74x164.txt
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*/
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priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
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priv->buffer = calloc(priv->nregs, sizeof(u8));
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if (!priv->buffer) {
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ret = -ENOMEM;
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goto free_str;
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}
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ret = fdtdec_get_byte_array(fdt, node, "registers-default",
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priv->buffer, priv->nregs);
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if (ret)
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dev_dbg(dev, "No registers-default property\n");
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ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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if (ret) {
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dev_dbg(dev, "No oe-pins property\n");
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}
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uc_priv->bank_name = str;
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uc_priv->gpio_count = priv->nregs * 8;
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ret = gen_74x164_write_conf(dev);
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if (ret)
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goto free_buf;
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dev_dbg(dev, "%s is ready\n", dev->name);
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return 0;
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free_buf:
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free(priv->buffer);
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free_str:
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free(str);
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return ret;
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}
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static const struct udevice_id gen_74x164_ids[] = {
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{ .compatible = "fairchild,74hc595" },
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{ }
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};
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U_BOOT_DRIVER(74x164) = {
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.name = "74x164",
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.id = UCLASS_GPIO,
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.ops = &gen_74x164_ops,
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.probe = gen_74x164_probe,
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.priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
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.of_match = gen_74x164_ids,
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};
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