86 lines
1.6 KiB
Plaintext
86 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
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#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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aliases {
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serial0 = &blsp1_uart1;
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};
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reserved-memory {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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smem_mem: smem_region: smem@87e00000 {
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reg = <0x87e00000 0x080000>;
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no-map;
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};
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tz@87e80000 {
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reg = <0x87e80000 0x180000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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reg = <0x1800000 0x60000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: qcom,tlmm@1000000 {
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compatible = "qcom,tlmm-ipq4019";
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reg = <0x1000000 0x300000>;
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u-boot,dm-pre-reloc;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
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bit-rate = <0xFF>;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <100>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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};
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};
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};
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