mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
136 lines
3.7 KiB
C
136 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* A83 specific clock code
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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clock_set_pll1(408000000);
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/* enable pll_hsic, default is 480M */
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writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
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writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
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while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
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/* switch to default 24MHz before changing to hsic */
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writel(0x0, &ccm->cci400_cfg);
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sdelay(50);
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writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
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sdelay(100);
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/* switch before changing pll6 */
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clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
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AHB1_CLK_SRC_OSC24M);
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
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writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
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writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
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writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
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/* timestamp */
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writel(1, 0x01720000);
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}
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#endif
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* uart clock source is apb2 */
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writel(APB2_CLK_SRC_OSC24M|
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APB2_CLK_RATE_N_1|
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APB2_CLK_RATE_M(1),
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&ccm->apb2_div);
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/* open the clock for uart */
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->apb2_reset_cfg,
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1 << (APB2_RESET_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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}
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#ifdef CONFIG_SPL_BUILD
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void clock_set_pll1(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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/* Switch to 24MHz clock while changing PLL1 */
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writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
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AXI_DIV_2 << AXI1_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
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CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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/* clk = 24*n/p, p is ignored if clock is >288MHz */
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
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CCM_PLL1_CTRL_N(clk / 24000000),
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&ccm->pll1_c0_cfg);
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while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
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CCM_PLL1_CTRL_N(clk / (24000000)),
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&ccm->pll1_c1_cfg);
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while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
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/* Switch CPU to PLL1 */
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writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
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AXI_DIV_2 << AXI1_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
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CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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}
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#endif
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void clock_set_pll5(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int div1 = 0, div2 = 0;
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/* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
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writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
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CCM_PLL5_CTRL_N(clk / (24000000)) |
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div2 << CCM_PLL5_DIV2_SHIFT |
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div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
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udelay(5500);
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}
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unsigned int clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll6_cfg);
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int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
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int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
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CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
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int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
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CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
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return 24000000 * n / div1 / div2;
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}
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