Lukas Auer c9056653ec riscv: move the AX25-specific implementation of flush_dcache_all ... The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-01-15 09:36:31 +08:00
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ax25	riscv: move the AX25-specific implementation of flush_dcache_all	2019-01-15 09:36:31 +08:00
qemu	riscv: Probe cpus during boot	2018-12-18 09:56:27 +08:00
cpu.c	riscv: Do some basic architecture level cpu initialization	2018-12-18 09:56:27 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: Save boot hart id to the global data	2018-12-18 09:56:27 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00