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![Shengzhou Liu](/assets/img/avatar_default.png)
The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
483 lines
12 KiB
C
483 lines
12 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include "../common/qixis.h"
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#include "../common/fman.h"
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#include "p3060qds_qixis.h"
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#define EMI_NONE 0xffffffff
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#define EMI1_RGMII1 0
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#define EMI1_SLOT1 1
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#define EMI1_SLOT2 2
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#define EMI1_SLOT3 3
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#define EMI1_RGMII2 4
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static int mdio_mux[NUM_FM_PORTS];
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static char *mdio_names[5] = {
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"P3060QDS_MDIO0",
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"P3060QDS_MDIO1",
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"P3060QDS_MDIO2",
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"P3060QDS_MDIO3",
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"P3060QDS_MDIO4",
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};
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/*
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* Mapping of all 18 SERDES lanes to board slots.
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* A value of '0' here means that the mapping must be determined
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* dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
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*/
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static u8 lane_to_slot[] = {
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4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
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};
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static char *p3060qds_mdio_name_for_muxval(u32 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u32 muxval)
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{
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struct mii_dev *bus;
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char *name = p3060qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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struct p3060qds_mdio {
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u32 muxval;
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struct mii_dev *realbus;
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};
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static void p3060qds_mux_mdio(u32 muxval)
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{
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u8 brdcfg4;
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << 4);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct p3060qds_mdio *priv = bus->priv;
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p3060qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct p3060qds_mdio *priv = bus->priv;
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p3060qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int p3060qds_mdio_reset(struct mii_dev *bus)
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{
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struct p3060qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int p3060qds_mdio_init(char *realbusname, u32 muxval)
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{
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struct p3060qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate P3060QDS MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate P3060QDS private data\n");
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free(bus);
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return -1;
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}
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bus->read = p3060qds_mdio_read;
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bus->write = p3060qds_mdio_write;
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bus->reset = p3060qds_mdio_reset;
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sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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if (mdio_mux[port] == EMI1_RGMII1)
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fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
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if (mdio_mux[port] == EMI1_RGMII2)
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fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
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if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
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|| (srds_prtcl == 0x6))) {
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switch (port) {
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case FM2_DTSEC4:
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fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
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break;
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case FM1_DTSEC4:
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fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
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break;
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default:
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break;
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}
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}
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if (mdio_mux[port] == EMI1_SLOT3) {
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switch (port) {
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case FM2_DTSEC3:
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fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
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break;
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case FM1_DTSEC3:
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fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
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break;
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default:
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break;
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}
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int i, lane, idx;
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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switch (mdio_mux[i]) {
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case EMI1_SLOT1:
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if (lane >= 14) {
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fdt_status_okay_by_alias(fdt,
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"emi1_slot1");
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fdt_status_disabled_by_alias(fdt,
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"emi1_slot1_bk1");
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} else {
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fdt_status_disabled_by_alias(fdt,
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"emi1_slot1");
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fdt_status_okay_by_alias(fdt,
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"emi1_slot1_bk1");
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}
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break;
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case EMI1_SLOT2:
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fdt_status_okay_by_alias(fdt, "emi1_slot2");
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break;
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case EMI1_SLOT3:
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fdt_status_okay_by_alias(fdt, "emi1_slot3");
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break;
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}
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break;
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case PHY_INTERFACE_MODE_RGMII:
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if (i == FM1_DTSEC1)
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fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
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if (i == FM1_DTSEC2)
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fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
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break;
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default:
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break;
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}
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}
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#if (CONFIG_SYS_NUM_FMAN == 2)
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for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
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idx = i - FM2_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
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if (lane >= 0) {
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switch (mdio_mux[i]) {
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case EMI1_SLOT1:
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if (lane >= 14)
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fdt_status_okay_by_alias(fdt,
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"emi1_slot1");
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else
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fdt_status_okay_by_alias(fdt,
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"emi1_slot1_bk1");
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break;
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case EMI1_SLOT2:
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fdt_status_okay_by_alias(fdt,
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"emi1_slot2");
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break;
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case EMI1_SLOT3:
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fdt_status_okay_by_alias(fdt,
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"emi1_slot3");
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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#endif
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}
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static void initialize_lane_to_slot(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int sdprtl = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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switch (sdprtl) {
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case 0x03:
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case 0x06:
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lane_to_slot[8] = 1;
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lane_to_slot[9] = lane_to_slot[8];
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lane_to_slot[16] = 5;
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lane_to_slot[17] = lane_to_slot[16];
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break;
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case 0x16:
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case 0x19:
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case 0x1C:
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lane_to_slot[8] = 5;
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lane_to_slot[9] = lane_to_slot[8];
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lane_to_slot[16] = 1;
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lane_to_slot[17] = lane_to_slot[16];
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break;
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default:
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puts("Invalid SerDes protocol for P3060QDS\n");
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break;
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}
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
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int i;
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struct fsl_pq_mdio_info dtsec_mdio_info;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int srds_cfg = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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initialize_lane_to_slot();
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/*
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* Set TBIPA on FM1@DTSEC1. This is needed for configurations
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* where FM1@DTSEC1 isn't used directly, since it provides
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* MDIO for other ports.
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*/
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out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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/* Register the 5 muxing front-ends to the MDIO buses */
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if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
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p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
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if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
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p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
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p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
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p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
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p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
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if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
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fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
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else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
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if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
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fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
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else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
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switch (srds_cfg) {
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case 0x03:
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case 0x06:
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
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break;
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case 0x16:
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case 0x19:
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case 0x1C:
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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default:
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puts("Invalid SerDes protocol for P3060QDS\n");
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break;
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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if (QIXIS_READ(present) & (1 << (slot - 1)))
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fm_disable_port(i);
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switch (slot) {
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case 1:
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mdio_mux[i] = EMI1_SLOT1;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 2:
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mdio_mux[i] = EMI1_SLOT2;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 3:
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mdio_mux[i] = EMI1_SLOT3;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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};
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break;
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case PHY_INTERFACE_MODE_RGMII:
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if (i == FM1_DTSEC1) {
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mdio_mux[i] = EMI1_RGMII1;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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} else if (i == FM1_DTSEC2) {
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mdio_mux[i] = EMI1_RGMII2;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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}
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break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if (CONFIG_SYS_NUM_FMAN == 2)
|
|
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
|
|
int idx = i - FM2_DTSEC1, lane, slot;
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot[lane];
|
|
if (QIXIS_READ(present) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
switch (slot) {
|
|
case 1:
|
|
mdio_mux[i] = EMI1_SLOT1;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 2:
|
|
mdio_mux[i] = EMI1_SLOT2;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 3:
|
|
mdio_mux[i] = EMI1_SLOT3;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
};
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif /* CONFIG_SYS_NUM_FMAN */
|
|
|
|
cpu_eth_init(bis);
|
|
#endif /* CONFIG_FMAN_ENET */
|
|
|
|
return pci_eth_init(bis);
|
|
}
|