mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
243 lines
5.5 KiB
C
243 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on original Kirorion5x_ood support which is
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _ORION5X_CPU_H
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#define _ORION5X_CPU_H
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#include <asm/system.h>
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#ifndef __ASSEMBLY__
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#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
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| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
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#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
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((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
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enum memory_bank {
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BANK0,
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BANK1,
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BANK2,
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BANK3
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};
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enum orion5x_cpu_winen {
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ORION5X_WIN_DISABLE,
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ORION5X_WIN_ENABLE
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};
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enum orion5x_cpu_target {
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ORION5X_TARGET_DRAM = 0,
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ORION5X_TARGET_DEVICE = 1,
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ORION5X_TARGET_PCI = 3,
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ORION5X_TARGET_PCIE = 4,
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ORION5X_TARGET_SASRAM = 9
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};
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enum orion5x_cpu_attrib {
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ORION5X_ATTR_DRAM_CS0 = 0x0e,
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ORION5X_ATTR_DRAM_CS1 = 0x0d,
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ORION5X_ATTR_DRAM_CS2 = 0x0b,
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ORION5X_ATTR_DRAM_CS3 = 0x07,
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ORION5X_ATTR_PCI_MEM = 0x59,
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ORION5X_ATTR_PCI_IO = 0x51,
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ORION5X_ATTR_PCIE_MEM = 0x59,
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ORION5X_ATTR_PCIE_IO = 0x51,
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ORION5X_ATTR_SASRAM = 0x00,
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ORION5X_ATTR_DEV_CS0 = 0x1e,
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ORION5X_ATTR_DEV_CS1 = 0x1d,
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ORION5X_ATTR_DEV_CS2 = 0x1b,
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ORION5X_ATTR_BOOTROM = 0x0f
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};
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/*
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* Device Address MAP BAR values
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*
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* All addresses and sizes not defined by board code
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* will be given default values here.
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*/
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#if !defined (ORION5X_ADR_PCIE_MEM)
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#define ORION5X_ADR_PCIE_MEM 0x90000000
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#endif
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#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
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#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000
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#endif
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#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
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#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0
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#endif
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#if !defined (ORION5X_SZ_PCIE_MEM)
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#define ORION5X_SZ_PCIE_MEM (128*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_PCIE_IO)
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#define ORION5X_ADR_PCIE_IO 0xf0000000
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#endif
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#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
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#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000
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#endif
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#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
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#define ORION5X_ADR_PCIE_IO_REMAP_HI 0
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#endif
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#if !defined (ORION5X_SZ_PCIE_IO)
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#define ORION5X_SZ_PCIE_IO (64*1024)
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#endif
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#if !defined (ORION5X_ADR_PCI_MEM)
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#define ORION5X_ADR_PCI_MEM 0x98000000
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#endif
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#if !defined (ORION5X_SZ_PCI_MEM)
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#define ORION5X_SZ_PCI_MEM (128*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_PCI_IO)
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#define ORION5X_ADR_PCI_IO 0xf0100000
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#endif
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#if !defined (ORION5X_SZ_PCI_IO)
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#define ORION5X_SZ_PCI_IO (64*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS0)
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#define ORION5X_ADR_DEV_CS0 0xfa000000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS0)
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#define ORION5X_SZ_DEV_CS0 (2*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS1)
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#define ORION5X_ADR_DEV_CS1 0xf8000000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS1)
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#define ORION5X_SZ_DEV_CS1 (32*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS2)
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#define ORION5X_ADR_DEV_CS2 0xfa800000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS2)
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#define ORION5X_SZ_DEV_CS2 (1*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_BOOTROM)
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#define ORION5X_ADR_BOOTROM 0xFFF80000
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#endif
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#if !defined (ORION5X_SZ_BOOTROM)
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#define ORION5X_SZ_BOOTROM (512*1024)
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#endif
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/*
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* PCIE registers are used for SoC device ID and revision
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*/
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#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
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#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
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/*
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* The following definitions are intended for identifying
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* the real device and revision on which u-boot is running
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* even if it was compiled only for a specific one. Thus,
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* these constants must not be considered chip-specific.
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*/
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/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
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#define MV88F5181L_REV_A0 8
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#define MV88F5181L_REV_A1 9
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D0 4
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/* Orion-1-90 (88F6183) */
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#define MV88F6183_DEV_ID 0x6183
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#define MV88F6183_REV_B0 3
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/*
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* read feroceon core extra feature register
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* using co-proc instruction
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*/
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static inline unsigned int readfr_extra_feature_reg(void)
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{
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unsigned int val;
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asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
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(val) : : "cc");
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return val;
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}
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/*
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* write feroceon core extra feature register
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* using co-proc instruction
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*/
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static inline void writefr_extra_feature_reg(unsigned int val)
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{
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asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
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(val) : "cc");
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isb();
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}
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/*
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* AHB to Mbus Bridge Registers
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* Source: 88F5182 User Manual, Appendix A, section A.4
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* Note: only windows 0 and 1 have remap capability.
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*/
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struct orion5x_win_registers {
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u32 ctrl;
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u32 base;
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u32 remap_lo;
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u32 remap_hi;
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};
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/*
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* CPU control and status Registers
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* Source: 88F5182 User Manual, Appendix A, section A.4
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*/
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struct orion5x_cpu_registers {
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u32 config; /*0x20100 */
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u32 ctrl_stat; /*0x20104 */
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u32 rstoutn_mask; /* 0x20108 */
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u32 sys_soft_rst; /* 0x2010C */
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u32 ahb_mbus_cause_irq; /* 0x20110 */
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u32 ahb_mbus_mask_irq; /* 0x20114 */
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};
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/*
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* DDR SDRAM Controller Address Decode Registers
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* Source: 88F5182 User Manual, Appendix A, section A.5.1
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*/
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struct orion5x_ddr_addr_decode_registers {
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u32 base;
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u32 size;
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};
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/*
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* functions
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*/
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u32 orion5x_device_id(void);
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u32 orion5x_device_rev(void);
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unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
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void timer_init_r(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ORION5X_CPU_H */
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