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https://github.com/brain-hackers/u-boot-brain
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8755d50706
Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
242 lines
5.8 KiB
ArmAsm
242 lines
5.8 KiB
ArmAsm
/*
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* Cache-handling routined for MIPS CPUs
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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#endif
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#define INDEX_BASE CKSEG0
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
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#if LONGSIZE == 4
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
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#endif
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.endm
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.macro cache_loop curr, end, line_sz, op
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10: cache \op, 0(\curr)
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PTR_ADDU \curr, \curr, \line_sz
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bne \curr, \end, 10b
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.endm
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.macro l1_info sz, line_sz, off
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.set push
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.set noat
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mfc0 $1, CP0_CONFIG, 1
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/* detect line size */
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srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
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andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
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move \sz, zero
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beqz \line_sz, 10f
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li \sz, 2
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sllv \line_sz, \sz, \line_sz
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/* detect associativity */
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srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
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andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
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addi \sz, \sz, 1
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/* sz *= line_sz */
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mul \sz, \sz, \line_sz
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/* detect log32(sets) */
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srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
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andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
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addiu $1, $1, 1
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andi $1, $1, 0x7
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/* sz <<= log32(sets) */
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sllv \sz, \sz, $1
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/* sz *= 32 */
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li $1, 32
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mul \sz, \sz, $1
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10:
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.set pop
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.endm
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they have good
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* parity. It must be called by the ROM before any cached locations are used
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* to prevent the possibility of data with bad parity being written to memory.
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*
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine will initialise an area of
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* memory starting at location zero to be used as a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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LEAF(mips_cache_reset)
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#ifdef CONFIG_SYS_ICACHE_SIZE
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li t2, CONFIG_SYS_ICACHE_SIZE
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li t8, CONFIG_SYS_CACHELINE_SIZE
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#else
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l1_info t2, t8, MIPS_CONF1_IA_SHIFT
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#endif
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#ifdef CONFIG_SYS_DCACHE_SIZE
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li t3, CONFIG_SYS_DCACHE_SIZE
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li t9, CONFIG_SYS_CACHELINE_SIZE
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#else
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l1_info t3, t9, MIPS_CONF1_DA_SHIFT
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#endif
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Determine the largest L1 cache size */
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#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
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#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
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li v0, CONFIG_SYS_ICACHE_SIZE
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#else
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li v0, CONFIG_SYS_DCACHE_SIZE
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#endif
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#else
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move v0, t2
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sltu t1, t2, t3
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movn v0, t3, t1
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#endif
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, CKSEG1
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
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/*
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* The TagLo registers used depend upon the CPU implementation, but the
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* architecture requires that it is safe for software to write to both
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* TagLo selects 0 & 2 covering supported cases.
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*/
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mtc0 zero, CP0_TAGLO
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mtc0 zero, CP0_TAGLO, 2
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/*
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* The caches are probably in an indeterminate state, so we force good
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* parity into them by doing an invalidate for each line. If
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* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
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* perform a load/fill & a further invalidate for each line, assuming
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* that the bottom of RAM (having just been cleared) will generate good
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* parity for the cache.
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*/
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/*
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* Initialize the I-cache first,
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*/
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blez t2, 1f
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, t2
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/* clear tag to invalidate */
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cache_loop t0, t1, t8, INDEX_STORE_TAG_I
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t8, FILL
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t8, INDEX_STORE_TAG_I
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#endif
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/*
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* then initialize D-cache.
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*/
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1: blez t3, 3f
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, t3
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/* clear all tags */
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cache_loop t0, t1, t9, INDEX_STORE_TAG_D
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* load from each line (in cached space) */
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PTR_LI t0, INDEX_BASE
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, t9
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t9, INDEX_STORE_TAG_D
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#endif
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3: jr ra
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END(mips_cache_reset)
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/*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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LEAF(dcache_status)
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_UNCACHED
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andi t0, t0, CONF_CM_CMASK
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move v0, zero
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beq t0, t1, 2f
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li v0, 1
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2: jr ra
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END(dcache_status)
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/*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_disable)
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/*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_enable)
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mfc0 t0, CP0_CONFIG
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ori t0, CONF_CM_CMASK
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xori t0, CONF_CM_CMASK
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ori t0, CONFIG_SYS_MIPS_CACHE_MODE
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_enable)
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