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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
267 lines
4.8 KiB
C
267 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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#include <common.h>
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#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
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static inline unsigned long CACHE_SET(unsigned char cache)
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{
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if (cache == ICACHE)
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return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
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>> ICM_CFG_OFF_ISET);
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else
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return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
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>> DCM_CFG_OFF_DSET);
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}
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static inline unsigned long CACHE_WAY(unsigned char cache)
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{
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if (cache == ICACHE)
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return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
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>> ICM_CFG_OFF_IWAY);
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else
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return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
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>> DCM_CFG_OFF_DWAY);
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}
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
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{
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if (cache == ICACHE)
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1);
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else
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1);
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}
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#endif
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#ifndef CONFIG_SYS_ICACHE_OFF
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void invalidate_icache_all(void)
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{
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unsigned long end, line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
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} while (end > 0);
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1I_VA_INVAL"
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:
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: "r"(start)
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);
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start += line_size;
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}
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}
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void icache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x01\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void icache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x01\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int icache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void dcache_wbinval_all(void)
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{
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unsigned long end, line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
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__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
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__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
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__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
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__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
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} while (end > 0);
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_WB"
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"\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
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);
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start += line_size;
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}
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
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);
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start += line_size;
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}
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}
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void dcache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x02\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void dcache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x02\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int dcache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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#else
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void dcache_wbinval_all(void)
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{
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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#endif
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void flush_dcache_all(void)
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{
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dcache_wbinval_all();
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}
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void cache_flush(void)
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{
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flush_dcache_all();
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invalidate_icache_all();
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr, addr + size);
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invalidate_icache_range(addr, addr + size);
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}
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