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https://github.com/brain-hackers/u-boot-brain
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6e5b12b614
Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008,2009
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *table)
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{
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u8 secondary;
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hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
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if (secondary != 0)
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pci_hose_scan_bus(hose, secondary);
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}
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static struct pci_config_table pci_ivybridge_config_table[] = {
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/* vendor, device, class, bus, dev, func */
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
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{}
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};
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->config_table = pci_ivybridge_config_table;
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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hose->region_count = 3;
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}
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