Masahiro Yamada c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC ... - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>		2016-09-23 01:00:23 +09:00
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arc	arc: Use -mcpu=XXX instead of obsolete -marcXXX	2016-09-16 12:12:26 +03:00
arm	ARM: uniphier: add PLL init code for LD11 SoC	2016-09-23 01:00:23 +09:00
avr32
blackfin
m68k	Kconfig: Move config IDENT_STRING to Kconfig	2016-09-20 09:30:23 -04:00
microblaze
mips	MIPS: Hang if run on a secondary CPU	2016-09-21 17:04:53 +02:00
nds32
nios2
openrisc
powerpc	PowerPC: Update MIP405/MIP405T to use Kconfig better	2016-09-20 09:30:25 -04:00
sandbox	cmd: Split 'bootz' and 'booti' out from 'bootm'	2016-08-20 11:35:07 -04:00
sh
sparc
x86	x86: efi: Fix EFI 64-bit payload build warnings	2016-08-30 09:26:05 +08:00
xtensa
.gitignore
Kconfig