mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-14 22:23:56 +09:00
8199a145c4
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies the microcode update data block encoded in Device Tree to the bootstrap processor but not passed to the other CPUs when multiprocessing is enabled. If the bootstrap processor successfully performs a microcode update from Device Tree, use the same data block for the other processors. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed build errors on edison and qemu-x86] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
112 lines
2.5 KiB
ArmAsm
112 lines
2.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <config.h>
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#include <asm/post.h>
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.globl car_init
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car_init:
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/*
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* Note: ebp holds the BIST value (built-in self test) so far, but ebp
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* will be destroyed through the FSP call, thus we have to test the
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* BIST value here before we call into FSP.
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*/
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test %ebp, %ebp
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jz car_init_start
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post_code(POST_BIST_FAILURE)
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jmp die
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car_init_start:
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post_code(POST_CAR_START)
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lea find_fsp_header_romstack, %esp
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jmp find_fsp_header
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find_fsp_header_ret:
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/* EAX points to FSP_INFO_HEADER */
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mov %eax, %ebp
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/* sanity test */
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cmp $CONFIG_FSP_ADDR, %eax
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jb die
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/* calculate TempRamInitEntry address */
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mov 0x30(%ebp), %eax
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add 0x1c(%ebp), %eax
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/* call FSP TempRamInitEntry to setup temporary stack */
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lea temp_ram_init_romstack, %esp
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jmp *%eax
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temp_ram_init_ret:
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addl $4, %esp
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cmp $0, %eax
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jnz car_init_fail
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post_code(POST_CAR_CPU_CACHE)
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/*
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* The FSP TempRamInit initializes the ecx and edx registers to
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* point to a temporary but writable memory range (Cache-As-RAM).
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* ecx: the start of this temporary memory range,
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* edx: the end of this range.
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*/
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/* stack grows down from top of CAR */
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movl %edx, %esp
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subl $4, %esp
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xor %esi, %esi
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jmp car_init_done
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.global fsp_init_done
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fsp_init_done:
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/*
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* We come here from fsp_continue() with eax pointing to the HOB list.
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* Save eax to esi temporarily.
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*/
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movl %eax, %esi
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car_init_done:
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/*
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* Re-initialize the ebp (BIST) to zero, as we already reach here
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* which means we passed BIST testing before.
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*/
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xorl %ebp, %ebp
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jmp car_init_ret
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car_init_fail:
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post_code(POST_CAR_FAILURE)
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die:
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hlt
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jmp die
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hlt
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/*
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* The function call before CAR initialization is tricky. It cannot
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* be called using the 'call' instruction but only the 'jmp' with
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* the help of a handcrafted stack in the ROM. The stack needs to
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* contain the function return address as well as the parameters.
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*/
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.balign 4
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find_fsp_header_romstack:
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.long find_fsp_header_ret
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.balign 4
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temp_ram_init_romstack:
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.long temp_ram_init_ret
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.long temp_ram_init_params
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temp_ram_init_params:
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_dt_ucode_base_size:
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/* These next two fields are filled in by ifdtool */
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.globl ucode_base
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ucode_base: /* Declared in microcode.h */
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.long 0 /* microcode base */
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.globl ucode_size
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ucode_size: /* Declared in microcode.h */
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.long 0 /* microcode size */
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.long CONFIG_SYS_MONITOR_BASE /* code region base */
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.long CONFIG_SYS_MONITOR_LEN /* code region size */
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