mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
217 lines
5.0 KiB
C
217 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* From coreboot src/soc/intel/braswell/include/soc/gpio.h
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*/
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#ifndef _BRASWELL_GPIO_H_
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#define _BRASWELL_GPIO_H_
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#include <asm/arch/iomap.h>
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enum mode_list {
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M0,
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M1,
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M2,
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M3,
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M4,
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M5,
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M6,
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M7,
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M8,
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M9,
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M10,
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M11,
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M12,
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M13,
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};
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enum int_select {
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L0,
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L1,
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L2,
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L3,
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L4,
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L5,
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L6,
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L7,
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L8,
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L9,
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L10,
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L11,
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L12,
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L13,
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L14,
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L15,
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};
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enum gpio_en {
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NATIVE = 0xff,
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GPIO = 0, /* Native, no need to set PAD_VALUE */
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GPO = 1, /* GPO, output only in PAD_VALUE */
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GPI = 2, /* GPI, input only in PAD_VALUE */
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HI_Z = 3,
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NA_GPO = 0,
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};
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enum gpio_state {
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LOW,
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HIGH,
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};
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enum en_dis {
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DISABLE, /* Disable */
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ENABLE, /* Enable */
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};
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enum int_type {
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INT_DIS,
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TRIG_EDGE_LOW,
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TRIG_EDGE_HIGH,
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TRIG_EDGE_BOTH,
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TRIG_LEVEL,
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};
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enum mask {
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MASKABLE,
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NON_MASKABLE,
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};
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enum glitch_cfg {
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GLITCH_DISABLE,
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EN_EDGE_DETECT,
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EN_RX_DATA,
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EN_EDGE_RX_DATA,
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};
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enum inv_rx_tx {
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NO_INVERSION = 0,
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INV_RX_ENABLE = 1,
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INV_TX_ENABLE = 2,
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INV_RX_TX_ENABLE = 3,
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INV_RX_DATA = 4,
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INV_TX_DATA = 8,
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};
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enum voltage {
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VOLT_3_3, /* Working on 3.3 Volts */
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VOLT_1_8, /* Working on 1.8 Volts */
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};
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enum hs_mode {
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DISABLE_HS, /* Disable high speed mode */
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ENABLE_HS, /* Enable high speed mode */
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};
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enum odt_up_dn {
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PULL_UP, /* On Die Termination Up */
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PULL_DOWN, /* On Die Termination Down */
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};
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enum odt_en {
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DISABLE_OD, /* On Die Termination Disable */
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ENABLE_OD, /* On Die Termination Enable */
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};
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enum pull_type {
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P_NONE = 0, /* Pull None */
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P_20K_L = 1, /* Pull Down 20K */
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P_5K_L = 2, /* Pull Down 5K */
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P_1K_L = 4, /* Pull Down 1K */
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P_20K_H = 9, /* Pull Up 20K */
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P_5K_H = 10, /* Pull Up 5K */
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P_1K_H = 12 /* Pull Up 1K */
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};
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enum bit {
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ONE_BIT = 1,
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TWO_BIT = 3,
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THREE_BIT = 7,
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FOUR_BIT = 15,
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FIVE_BIT = 31,
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SIX_BIT = 63,
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SEVEN_BIT = 127,
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EIGHT_BIT = 255
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};
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enum gpe_config {
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GPE,
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SMI,
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SCI,
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};
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enum community {
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SOUTHWEST = 0x0000,
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NORTH = 0x8000,
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EAST = 0x10000,
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SOUTHEAST = 0x18000,
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VIRTUAL = 0x20000,
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};
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#define NA 0xff
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#define TERMINATOR 0xffffffff
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#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
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odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
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.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
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(((hysctl) != NA) ? hysctl << 24 : 0) | \
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(((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
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(((hs_mode) != NA) ? hs_mode << 19 : 0) | \
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(((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
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(((odt_en) != NA) ? odt_en << 17 : 0) | \
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(curr_src_str)), \
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.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
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(((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
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(((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
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(((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
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(((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
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(((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
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(THREE_BIT)), \
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.misc = ((rcomp == ENABLE) ? 1 : 0) , \
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.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
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((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
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(0x80 * family_no) + 0x1080) : 0) , \
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.name = 0 \
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}
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#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
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gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
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int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
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mmio_offset, community_offset) { \
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.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
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(((glitch) != NA) ? (glitch << 26) : 0) | \
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(((term) != NA) ? (term << 20) : 0) | \
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(((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
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((mode << 16))) | \
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(((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
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(((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
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(((gpio_state) == HIGH) ? 2 : 0)), \
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.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
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(((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
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(((term) != NA) ? (FOUR_BIT << 20) : 0) | \
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(FIVE_BIT << 15) | \
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(((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
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(((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
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(((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
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.confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
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(((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
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(((open_drain) != NA) ? open_drain << 3 : 0) | \
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(((int_type) != NA) ? int_type : 0)), \
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.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
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(((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
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(((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
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(((int_type) != NA) ? THREE_BIT : 0)), \
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.community = community_offset, \
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.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
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((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
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community_offset + mmio_offset) : 0), \
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.name = 0, \
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.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
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(((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
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(((int_mask) != NA) ? (int_mask << 3) : 0)) | \
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(((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
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}
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#endif /* _BRASWELL_GPIO_H_ */
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