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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*/
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#include <common.h>
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#include <asm/cacheops.h>
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#ifdef CONFIG_MIPS_L2_CACHE
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#include <asm/cm.h>
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#endif
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void probe_l2(void)
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{
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#ifdef CONFIG_MIPS_L2_CACHE
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unsigned long conf2, sl;
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bool l2c = false;
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if (!(read_c0_config1() & MIPS_CONF_M))
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return;
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conf2 = read_c0_config2();
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if (__mips_isa_rev >= 6) {
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l2c = conf2 & MIPS_CONF_M;
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if (l2c)
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l2c = read_c0_config3() & MIPS_CONF_M;
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if (l2c)
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l2c = read_c0_config4() & MIPS_CONF_M;
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if (l2c)
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l2c = read_c0_config5() & MIPS_CONF5_L2C;
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}
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if (l2c && config_enabled(CONFIG_MIPS_CM)) {
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gd->arch.l2_line_size = mips_cm_l2_line_size();
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} else if (l2c) {
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/* We don't know how to retrieve L2 config on this system */
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BUG();
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} else {
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sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
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gd->arch.l2_line_size = sl ? (2 << sl) : 0;
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}
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#endif
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}
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void mips_cache_probe(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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unsigned long conf1, il, dl;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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gd->arch.l1i_line_size = il ? (2 << il) : 0;
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gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
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#endif
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probe_l2();
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}
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static inline unsigned long icache_line_size(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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return gd->arch.l1i_line_size;
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#else
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return CONFIG_SYS_ICACHE_LINE_SIZE;
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#endif
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}
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static inline unsigned long dcache_line_size(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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return gd->arch.l1d_line_size;
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#else
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return CONFIG_SYS_DCACHE_LINE_SIZE;
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#endif
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}
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static inline unsigned long scache_line_size(void)
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{
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#ifdef CONFIG_MIPS_L2_CACHE
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return gd->arch.l2_line_size;
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#else
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return 0;
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#endif
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}
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#define cache_loop(start, end, lsize, ops...) do { \
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const void *addr = (const void *)(start & ~(lsize - 1)); \
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const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
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const unsigned int cache_ops[] = { ops }; \
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unsigned int i; \
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\
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if (!lsize) \
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break; \
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\
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for (; addr <= aend; addr += lsize) { \
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for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
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mips_cache(cache_ops[i], addr); \
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} \
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} while (0)
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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unsigned long slsize = scache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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if ((ilsize == dlsize) && !slsize) {
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/* flush I-cache & D-cache simultaneously */
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cache_loop(start_addr, start_addr + size, ilsize,
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HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
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goto ops_done;
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}
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/* flush D-cache */
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cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
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/* flush L2 cache */
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cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
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/* flush I-cache */
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cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
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ops_done:
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/* ensure cache ops complete before any further memory accesses */
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sync();
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/* ensure the pipeline doesn't contain now-invalid instructions */
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instruction_hazard_barrier();
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long slsize = scache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
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/* flush L2 cache */
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cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
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/* ensure cache ops complete before any further memory accesses */
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sync();
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long slsize = scache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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/* invalidate L2 cache */
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cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
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cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
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/* ensure cache ops complete before any further memory accesses */
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sync();
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}
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