mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 19:39:44 +09:00
8ca78f2c89
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:
...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
174 lines
5.5 KiB
C
174 lines
5.5 KiB
C
/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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/*
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* 85xx and 86xx share naming conventions, but different layout.
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* Correlate names to CPU-specific values to share common
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* PCI code.
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*/
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#if defined(CONFIG_MPC85xx)
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#define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
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#define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
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#define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
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#define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL
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#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT
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#define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA
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#define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT
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#elif defined(CONFIG_MPC86xx)
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#define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1
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#define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2
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#define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */
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#define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL
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#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT
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#define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA
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#define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT
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#endif
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void pci_init_board(void)
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{
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struct fsl_pci_info pci_info[3];
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep;
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__maybe_unused int pcie_configured;
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#elif defined(CONFIG_MPC86xx)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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#endif
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u32 devdisr = in_be32(&gur->devdisr);
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u32 pordevsr = in_be32(&gur->pordevsr);
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__maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
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MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
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#ifdef CONFIG_PCI1
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uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
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uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
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uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
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uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
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pci_32 ? 32 : 64,
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pcix ? "PCIX" : "PCI",
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pci_spd_norm ? ">=" : "<=",
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pcix ? freq * 2 : freq,
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pcie_ep ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI1: disabled\n");
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}
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#elif defined CONFIG_MPC8548
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/* PCI1 not present on MPC8572 */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
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#endif
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf("PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
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#endif /* CONFIG_PCIE2 */
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#ifdef CONFIG_PCIE3
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf("PCIE3: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf("PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
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#endif /* CONFIG_PCIE3 */
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_pci_setup(void *blob, bd_t *bd)
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{
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FT_FSL_PCI_SETUP;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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