mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
80bf2bb501
This patch adds support for the HP Jornada flashboards that were made in 2008. Older flashroms should work if memory registers are adjusted. Signed-off-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Adpted for TEXT_BASE -> CONFIG_SYS_TEXT_BASE rename. Removed now redundant board/jornada/config.mk file. Removed unused empty jornada_init() function to silence "jornada.c:35: warning: 'jornada_init' defined but not used" Signed-off-by: Wolfgang Denk <wd@denx.de>
211 lines
4.9 KiB
ArmAsm
211 lines
4.9 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* 2004 (c) MontaVista Software, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "config.h"
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#include "version.h"
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/*-----------------------------------------------------------------------
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* Board defines:
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*/
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#define MDCNFG 0x00
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#define MDCAS00 0x04
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#define MDCAS01 0x08
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#define MDCAS02 0x0C
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#define MSC0 0x10
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#define MSC1 0x14
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#define MECR 0x18
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#define MDREFR 0x1C
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#define MDCAS20 0x20
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#define MDCAS21 0x24
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#define MDCAS22 0x28
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#define MSC2 0x2C
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#define SMCNFG 0x30
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#define GPDR 0x04
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#define GPSR 0x08
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#define GPCR 0x0C
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#define GAFR 0x1C
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#define PPDR 0x00
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#define PPSR 0x04
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#define PPAR 0x08
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#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
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#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
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#define MDREFR_K0DB2 (1 << 18)
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#define MDREFR_K1DB2 (1 << 22)
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#define MDREFR_K2DB2 (1 << 26)
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#define MDREFR_K0RUN (1 << 17)
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#define MDREFR_K1RUN (1 << 21)
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#define MDREFR_K2RUN (1 << 25)
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#define MDREFR_SLFRSH (1 << 31)
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#define MDREFR_E1PIN (1 << 20)
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#define PSSR 0x04
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#define PSSR_DH 0x00000008
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#define POSR 0x08
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#define RCSR 0x04
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/*-----------------------------------------------------------------------
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* Setup parameters for the board:
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*/
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MEM_BASE: .long 0xa0000000
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MEM_START: .long 0xc0000000
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PWR_BASE: .word 0x90020000
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RST_BASE: .long 0x90030000
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PPC_BASE: .long 0x90060000
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GPIO_BASE: .long 0x90040000
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IC_BASE: .word 0x90050000
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cpuspeed: .word 0xa0
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/* calculated from old blob bootloader */
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mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
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mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
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mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
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mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
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msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
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msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
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mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
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mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
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mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
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mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
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mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
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msc2: .long 0x201d2959 /* msc2 0x201d2959 */
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smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
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pin_set_out: .long 0x37ff70
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pin_set_dir: .long 0x11480
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gpdr_set: .long 0x0B3A0900
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gpsr_set: .long 0x02100800
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gpcr_set: .long 0x092A0100
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gafr_set: .long 0x08600000
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.globl lowlevel_init
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lowlevel_init:
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/* set output and direction of pins */
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ldr r0, PPC_BASE
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ldr r1, pin_set_out
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str r1, [r0, #PPSR]
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ldr r1, pin_set_dir
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str r1, [r0, #PPDR]
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/* Setting up the memory and stuff */
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/***********************************/
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ldr r0, MEM_BASE
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ldr r1, mdcnfg
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str r1, [r0, #MDCNFG]
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ldr r1, mdcas00
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str r1, [r0, #MDCAS00]
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ldr r1, mdcas01
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str r1, [r0, #MDCAS01]
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ldr r1, mdcas02
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str r1, [r0, #MDCAS02]
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ldr r1, mdcas20
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str r1, [r0, #MDCAS20]
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ldr r1, mdcas21
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str r1, [r0, #MDCAS21]
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ldr r1, mdcas22
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str r1, [r0, #MDCAS22]
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/* clear kxDB2 */
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_K0DB2
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bic r2, r2, #MDREFR_K1DB2
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bic r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_TRASR(7)
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mov r4, #0x2000
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spin: subs r4, r4, #1
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bne spin
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ldr r1, PWR_BASE
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mov r2, #PSSR_DH
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str r2, [r1, #PSSR]
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_K0DB2
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bic r2, r2, #MDREFR_K1DB2
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bic r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_TRASR(7)
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orr r2, r2, #MDREFR_DRI(12)
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orr r2, r2, #MDREFR_K0DB2
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orr r2, r2, #MDREFR_K1DB2
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orr r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_K0RUN
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orr r2, r2, #MDREFR_K1RUN
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orr r2, r2, #MDREFR_K2RUN
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_SLFRSH
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_E1PIN
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str r2, [r0, #MDREFR]
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ldr r2, MEM_START
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.rept 8
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ldr r3, [r2]
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.endr
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ldr r1, msc0
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str r1, [r0, #MSC0]
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ldr r1, msc1
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str r1, [r0, #MSC1]
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ldr r1, msc2
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str r1, [r0, #MSC2]
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ldr r1, smcnfg
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str r1, [r0, #SMCNFG]
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ldr r1, mdcnfg
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str r1, [r0, #MDCNFG]
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ldr r1, mecr
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str r1, [r0, #MECR]
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/* enable SDRAM */
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orr r1, r1, #0x00000001
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str r1, [r0, #MDCNFG]
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mov pc, lr
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