mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6d82517836
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
48 lines
1.7 KiB
Plaintext
48 lines
1.7 KiB
Plaintext
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Simple steps used to test the QSPI at U-Boot
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For #1, build the patched U-Boot and load MLO/u-boot.img
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----------------------------------
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Boot from another medium like MMC
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----------------------------------
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U-Boot# mmc dev 0
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mmc0 is current device
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U-Boot# fatload mmc 0 0x82000000 MLO
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reading MLO
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55872 bytes read in 8 ms (6.7 MiB/s)
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U-Boot# fatload mmc 0 0x83000000 u-boot.img
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reading u-boot.img
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248600 bytes read in 19 ms (12.5 MiB/s)
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--------------------------------------------------
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Commands to erase/write u-boot/mlo to flash device
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--------------------------------------------------
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U-Boot# sf probe 0
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SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
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U-Boot# sf erase 0 0x10000
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SF: 65536 bytes @ 0x0 Erased: OK
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U-Boot# sf erase 0x20000 0x10000
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SF: 65536 bytes @ 0x20000 Erased: OK
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U-Boot# sf erase 0x30000 0x10000
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SF: 65536 bytes @ 0x30000 Erased: OK
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U-Boot# sf erase 0x40000 0x10000
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SF: 65536 bytes @ 0x40000 Erased: OK
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U-Boot# sf erase 0x50000 0x10000
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SF: 65536 bytes @ 0x50000 Erased: OK
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U-Boot# sf erase 0x60000 0x10000
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SF: 65536 bytes @ 0x60000 Erased: OK
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U-Boot# sf write 82000000 0 0x10000
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SF: 65536 bytes @ 0x0 Written: OK
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U-Boot# sf write 83000000 0x20000 0x60000
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SF: 393216 bytes @ 0x20000 Written: OK
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For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
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on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
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then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
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find a U-Boot image header at offset 0x20000 (set in the config file)
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and proceeds to load that image using the U-Boot image payload offset/size
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from the header. It will then start U-Boot.
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