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https://github.com/brain-hackers/u-boot-brain
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a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_H
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#define LPDDR4_H
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#include "lpddr4_ctl_regs.h"
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#include "lpddr4_sanity.h"
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#ifdef CONFIG_K3_AM64_DDRSS
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#include "lpddr4_16bit.h"
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#include "lpddr4_16bit_sanity.h"
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#else
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#include "lpddr4_32bit.h"
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#include "lpddr4_32bit_sanity.h"
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#endif
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#ifdef REG_WRITE_VERIF
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#include "lpddr4_ctl_regs_rw_masks.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PRODUCT_ID (0x1046U)
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#define LPDDR4_BIT_MASK (0x1U)
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#define BYTE_MASK (0xffU)
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#define NIBBLE_MASK (0xfU)
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#define WORD_SHIFT (32U)
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#define WORD_MASK (0xffffffffU)
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#define SLICE_WIDTH (0x100)
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#define CTL_OFFSET 0
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#define PI_OFFSET (((u32)1) << 11)
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#define PHY_OFFSET (((u32)1) << 12)
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#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
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#define PLL_READY (0x3U)
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#define IO_CALIB_DONE ((u32)0x1U << 23U)
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#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
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#define IO_CALIB_STATE ((u32)0xBU << 28U)
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#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
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#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
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#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
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#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
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#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
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#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
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#define CDN_TRUE 1U
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#define CDN_FALSE 0U
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void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
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volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
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u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
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bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
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void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
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u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
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void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
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u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
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u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPDDR4_H */
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