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https://github.com/brain-hackers/u-boot-brain
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18fb0e3cae
For most PPC platforms, they will call the first get_clocks() in init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is then defined to call the second get_clocks(), which should be redundant for PPC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
96 lines
2.1 KiB
C
96 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX7.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX7_COMMON_H
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#define __MX7_COMMON_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/imx-common/gpio.h>
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#ifndef CONFIG_MX7
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#define CONFIG_MX7
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#endif
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/* Timer settings */
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_SYSCOUNTER_TIMER
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define CONFIG_SYS_FSL_CLK
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/* Enable iomux-lpsr support */
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#define CONFIG_IOMUX_LPSR
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#define CONFIG_IMX_FIXED_IVT_OFFSET
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_ROM_UNIFIED_SECTIONS
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_LOADADDR 0x80800000
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#define CONFIG_SYS_TEXT_BASE 0x87800000
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#ifndef CONFIG_BOOTDELAY
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#define CONFIG_BOOTDELAY 3
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#endif
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* Filesystems and image support */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_EXT4_WRITE
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#define CONFIG_CMD_FAT
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/* Miscellaneous configurable options */
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#undef CONFIG_CMD_IMLS
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 512
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#ifndef CONFIG_SYS_DCACHE_OFF
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#define CONFIG_CMD_CACHE
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#endif
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/* GPIO */
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#define CONFIG_MXC_GPIO
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#define CONFIG_CMD_GPIO
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/* UART */
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
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/* MMC */
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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/* Fuses */
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#define CONFIG_CMD_FUSE
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#define CONFIG_MXC_OCOTP
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#endif
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