mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 20:26:17 +09:00
9171fc8172
All of the duplicated code for Blackfin processors and boot modes have been unified. After all, the core is the same for all processors, just the peripheral set differs (which gets handled in the drivers). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
354 lines
9.8 KiB
C
354 lines
9.8 KiB
C
/*
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* initcode.c - Initialize the processor. This is usually entails things
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* like external memory, voltage regulators, etc... Note that this file
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* cannot make any function calls as it may be executed all by itself by
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* the Blackfin's bootrom in LDR format.
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*
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* Copyright (c) 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <config.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/bootrom.h>
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#include <asm/mach-common/bits/ebiu.h>
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#include <asm/mach-common/bits/pll.h>
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#include <asm/mach-common/bits/uart.h>
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#define BFIN_IN_INITCODE
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#include "serial.h"
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__attribute__((always_inline))
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static inline uint32_t serial_init(void)
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{
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#ifdef __ADSPBF54x__
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# ifdef BFIN_BOOT_UART_USE_RTS
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# define BFIN_UART_USE_RTS 1
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# else
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# define BFIN_UART_USE_RTS 0
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# endif
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if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
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size_t i;
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/* force RTS rather than relying on auto RTS */
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bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
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/* Wait for the line to clear up. We cannot rely on UART
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* registers as none of them reflect the status of the RSR.
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* Instead, we'll sleep for ~10 bit times at 9600 baud.
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* We can precalc things here by assuming boot values for
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* PLL rather than loading registers and calculating.
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* baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
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* EDB0 = 0
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* Divisor = (SCLK / baud) / 16
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* SCLK = baud * 16 * Divisor
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* SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
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* CCLK = (16 * Divisor * 5) * (9600 / 10)
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* In reality, this will probably be just about 1 second delay,
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* so assuming 9600 baud is OK (both as a very low and too high
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* speed as this will buffer things enough).
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*/
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#define _NUMBITS (10) /* how many bits to delay */
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#define _LOWBAUD (9600) /* low baud rate */
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#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
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#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
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#define _NUMINS (3) /* how many instructions in loop */
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#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
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i = _CCLK;
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while (i--)
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asm volatile("" : : : "memory");
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}
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#endif
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uint32_t old_baud = serial_early_get_baud();
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if (BFIN_DEBUG_EARLY_SERIAL) {
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serial_early_init();
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/* If the UART is off, that means we need to program
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* the baud rate ourselves initially.
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*/
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if (!old_baud) {
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old_baud = CONFIG_BAUDRATE;
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serial_early_set_baud(CONFIG_BAUDRATE);
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}
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}
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return old_baud;
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}
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__attribute__((always_inline))
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static inline void serial_deinit(void)
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{
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#ifdef __ADSPBF54x__
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if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
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/* clear forced RTS rather than relying on auto RTS */
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bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
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}
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#endif
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}
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/* We need to reset the baud rate when we have early debug turned on
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* or when we are booting over the UART.
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* XXX: we should fix this to calc the old baud and restore it rather
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* than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
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* to figure out how to avoid the division in the baud calc ...
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*/
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__attribute__((always_inline))
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static inline void serial_reset_baud(uint32_t baud)
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{
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if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
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return;
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#ifndef CONFIG_LDR_LOAD_BAUD
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# define CONFIG_LDR_LOAD_BAUD 115200
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#endif
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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serial_early_set_baud(baud);
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else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
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serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
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else
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serial_early_set_baud(CONFIG_BAUDRATE);
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}
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__attribute__((always_inline))
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static inline void serial_putc(char c)
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{
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if (!BFIN_DEBUG_EARLY_SERIAL)
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return;
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if (c == '\n')
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*pUART_THR = '\r';
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*pUART_THR = c;
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while (!(*pUART_LSR & TEMT))
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continue;
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}
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/* Max SCLK can be 133MHz ... dividing that by 4 gives
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* us a freq of 33MHz for SPI which should generally be
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* slow enough for the slow reads the bootrom uses.
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*/
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#ifndef CONFIG_SPI_BAUD_INITBLOCK
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# define CONFIG_SPI_BAUD_INITBLOCK 4
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#endif
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/* PLL_DIV defines */
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#ifndef CONFIG_PLL_DIV_VAL
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# if (CONFIG_CCLK_DIV == 1)
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# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
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# elif (CONFIG_CCLK_DIV == 2)
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# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
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# elif (CONFIG_CCLK_DIV == 4)
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# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
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# elif (CONFIG_CCLK_DIV == 8)
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# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
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# else
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# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
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# endif
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# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
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#endif
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#ifndef CONFIG_PLL_LOCKCNT_VAL
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# define CONFIG_PLL_LOCKCNT_VAL 0x0300
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#endif
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#ifndef CONFIG_PLL_CTL_VAL
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# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9))
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#endif
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#ifndef CONFIG_EBIU_RSTCTL_VAL
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# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
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#endif
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#ifndef CONFIG_EBIU_MBSCTL_VAL
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# define CONFIG_EBIU_MBSCTL_VAL 0
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#endif
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/* Make sure our voltage value is sane so we don't blow up! */
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#ifndef CONFIG_VR_CTL_VAL
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# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
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# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
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# define CCLK_VLEV_120 400000000
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# define CCLK_VLEV_125 533000000
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# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
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# define CCLK_VLEV_120 401000000
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# define CCLK_VLEV_125 401000000
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# elif defined(__ADSPBF561__)
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# define CCLK_VLEV_120 300000000
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# define CCLK_VLEV_125 501000000
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# endif
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# if BFIN_CCLK < CCLK_VLEV_120
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# define CONFIG_VR_CTL_VLEV VLEV_120
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# elif BFIN_CCLK < CCLK_VLEV_125
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# define CONFIG_VR_CTL_VLEV VLEV_125
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# else
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# define CONFIG_VR_CTL_VLEV VLEV_130
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# endif
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# if defined(__ADSPBF52x__) /* TBD; use default */
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# undef CONFIG_VR_CTL_VLEV
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# define CONFIG_VR_CTL_VLEV VLEV_110
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# elif defined(__ADSPBF54x__) /* TBD; use default */
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# undef CONFIG_VR_CTL_VLEV
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# define CONFIG_VR_CTL_VLEV VLEV_120
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# endif
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# ifdef CONFIG_BFIN_MAC
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# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
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# else
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# define CONFIG_VR_CTL_CLKBUF 0
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# endif
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# if defined(__ADSPBF52x__)
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# define CONFIG_VR_CTL_FREQ FREQ_1000
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# else
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# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
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# endif
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# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
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#endif
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__attribute__((saveall))
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void initcode(ADI_BOOT_DATA *bootstruct)
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{
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uint32_t old_baud = serial_init();
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#ifdef CONFIG_HW_WATCHDOG
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# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
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# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
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# endif
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/* Program the watchdog with an initial timeout of ~20 seconds.
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* Hopefully that should be long enough to load the u-boot LDR
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* (from wherever) and then the common u-boot code can take over.
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* In bypass mode, the start.S would have already set a much lower
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* timeout, so don't clobber that.
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*/
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if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
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bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
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bfin_write_WDOG_CTL(0);
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}
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#endif
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serial_putc('S');
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/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
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* fast read, so we need to slow down the SPI clock a lot more during
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* boot. Once we switch over to u-boot's SPI flash driver, we'll
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* increase the speed appropriately.
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*/
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#ifdef SPI0_BAUD
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bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
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#else
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bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
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#endif
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serial_putc('B');
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/* Disable all peripheral wakeups except for the PLL event. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(1);
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bfin_write_SIC_IWR1(0);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(0);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(1);
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bfin_write_SICA_IWR1(0);
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#else
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bfin_write_SIC_IWR(1);
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#endif
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serial_putc('L');
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bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
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serial_putc('A');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
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serial_putc('!');
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bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
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asm("idle;");
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}
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serial_putc('C');
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bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
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serial_putc('K');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
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serial_putc('!');
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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}
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/* Since we've changed the SCLK above, we may need to update
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* the UART divisors (UART baud rates are based on SCLK).
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*/
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serial_reset_baud(old_baud);
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serial_putc('F');
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/* Program the async banks controller. */
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bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
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bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
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bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
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#ifdef EBIU_MODE
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/* Not all parts have these additional MMRs. */
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bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
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bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
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bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
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#endif
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serial_putc('I');
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/* Program the external memory controller. */
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#ifdef EBIU_RSTCTL
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
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bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
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bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
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bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
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# ifdef CONFIG_EBIU_DDRCTL3_VAL
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/* default is disable, so don't need to force this */
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bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
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# endif
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#else
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bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
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bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
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bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
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#endif
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serial_putc('N');
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/* Restore all peripheral wakeups. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(-1);
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bfin_write_SIC_IWR1(-1);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(-1);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(-1);
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bfin_write_SICA_IWR1(-1);
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#else
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bfin_write_SIC_IWR(-1);
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#endif
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serial_putc('>');
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serial_putc('\n');
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serial_deinit();
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}
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