mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6d0e34bf4e
The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* Marvell SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <linux/mbus.h>
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#define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
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#define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
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static void sdhci_mvebu_mbus_config(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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int i;
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dram = mvebu_mbus_dram_info();
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for (i = 0; i < 4; i++) {
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writel(0, base + SDHCI_WINDOW_CTRL(i));
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writel(0, base + SDHCI_WINDOW_BASE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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/* Write size, attributes and target id to control register */
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writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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base + SDHCI_WINDOW_CTRL(i));
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/* Write base address to base register */
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writel(cs->base, base + SDHCI_WINDOW_BASE(i));
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}
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}
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static struct sdhci_ops mv_ops;
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#if defined(CONFIG_SHEEVA_88SV331xV5)
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#define SD_CE_ATA_2 0xEA
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#define MMC_CARD 0x1000
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#define MMC_WIDTH 0x0100
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static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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struct mmc *mmc = host->mmc;
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u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
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if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
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if (mmc->bus_width == 8)
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writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
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else
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writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
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}
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writeb(val, host->ioaddr + reg);
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}
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#else
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#define mv_sdhci_writeb NULL
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#endif /* CONFIG_SHEEVA_88SV331xV5 */
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#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
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static char *MVSDH_NAME = "mv_sdh";
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int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
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{
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struct sdhci_host *host = NULL;
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host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
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if (!host) {
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printf("sdh_host malloc fail!\n");
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return -ENOMEM;
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}
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host->name = MVSDH_NAME;
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host->ioaddr = (void *)regbase;
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host->quirks = quirks;
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host->max_clk = max_clk;
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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memset(&mv_ops, 0, sizeof(struct sdhci_ops));
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mv_ops.write_b = mv_sdhci_writeb;
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host->ops = &mv_ops;
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#endif
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if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
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/* Configure SDHCI MBUS mbus bridge windows */
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sdhci_mvebu_mbus_config((void __iomem *)regbase);
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}
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return add_sdhci(host, 0, min_clk);
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}
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