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https://github.com/brain-hackers/u-boot-brain
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6ce383640c
So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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| .. | ||
| ag101p_timer.c | ||
| altera_timer.c | ||
| arc_timer.c | ||
| ast_timer.c | ||
| atcpit100_timer.c | ||
| atmel_pit_timer.c | ||
| cadence-ttc.c | ||
| dw-apb-timer.c | ||
| Kconfig | ||
| Makefile | ||
| mpc83xx_timer.c | ||
| omap-timer.c | ||
| rockchip_timer.c | ||
| sandbox_timer.c | ||
| sti-timer.c | ||
| stm32_timer.c | ||
| timer-uclass.c | ||
| tsc_timer.c | ||