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https://github.com/brain-hackers/u-boot-brain
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![Ley Foon Tan](/assets/img/avatar_default.png)
A mailbox command contains 1-u32 header + arguments. The "len" variable only contains the length of the arguments, but not the 1-u32 header. Include the length of header when checking the ring buffer space to prevent off-by-one error. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
428 lines
9.9 KiB
C
428 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/secure.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MBOX_READL(reg) \
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readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
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#define MBOX_WRITEL(data, reg) \
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writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
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#define MBOX_READ_RESP_BUF(rout) \
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MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
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#define MBOX_WRITE_CMD_BUF(data, cin) \
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MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
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static __always_inline int mbox_polling_resp(u32 rout)
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{
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u32 rin;
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unsigned long i = ~0;
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while (i) {
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rin = MBOX_READL(MBOX_RIN);
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if (rout != rin)
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return 0;
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i--;
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}
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return -ETIMEDOUT;
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}
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/* Check for available slot and write to circular buffer.
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* It also update command valid offset (cin) register.
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*/
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static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
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u32 *arg)
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{
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u32 cin;
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u32 cout;
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u32 i;
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cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
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cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
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/* if command buffer is full or not enough free space
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* to fit the data. Note, len is in u32 unit.
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*/
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if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
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((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
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MBOX_CMD_BUFFER_SIZE) < (len + 1))
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return -ENOMEM;
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/* write header to circular buffer */
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MBOX_WRITE_CMD_BUF(header, cin++);
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/* wrapping around when it reach the buffer size */
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cin %= MBOX_CMD_BUFFER_SIZE;
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/* write arguments */
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for (i = 0; i < len; i++) {
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MBOX_WRITE_CMD_BUF(arg[i], cin++);
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/* wrapping around when it reach the buffer size */
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cin %= MBOX_CMD_BUFFER_SIZE;
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}
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/* write command valid offset */
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MBOX_WRITEL(cin, MBOX_CIN);
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return 0;
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}
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/* Check the command and fill it into circular buffer */
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static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
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u8 is_indirect, u32 len,
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u32 *arg)
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{
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u32 header;
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int ret;
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/* Total length is command + argument length */
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if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
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return -EINVAL;
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if (cmd > MBOX_MAX_CMD_INDEX)
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return -EINVAL;
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header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
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(is_indirect) ? 1 : 0, cmd);
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ret = mbox_fill_cmd_circular_buff(header, len, arg);
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return ret;
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}
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/* Send command only without waiting for responses from SDM */
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static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
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u8 is_indirect, u32 len,
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u32 *arg)
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{
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int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
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/* write doorbell */
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MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
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return ret;
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}
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/* Return number of responses received in buffer */
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static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
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{
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u32 rin;
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u32 rout;
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u32 resp_len = 0;
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/* clear doorbell from SDM if it was SET */
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if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
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MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
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/* read current response offset */
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rout = MBOX_READL(MBOX_ROUT);
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/* read response valid offset */
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rin = MBOX_READL(MBOX_RIN);
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while (rin != rout && (resp_len < resp_buf_max_len)) {
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/* Response received */
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if (resp_buf)
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resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
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rout++;
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/* wrapping around when it reach the buffer size */
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rout %= MBOX_RESP_BUFFER_SIZE;
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/* update next ROUT */
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MBOX_WRITEL(rout, MBOX_ROUT);
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}
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return resp_len;
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}
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/* Support one command and up to 31 words argument length only */
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static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
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u32 len, u32 *arg, u8 urgent,
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u32 *resp_buf_len,
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u32 *resp_buf)
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{
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u32 rin;
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u32 resp;
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u32 rout;
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u32 status;
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u32 resp_len;
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u32 buf_len;
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int ret;
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if (urgent) {
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/* Read status because it is toggled */
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status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
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/* Write urgent command to urgent register */
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MBOX_WRITEL(cmd, MBOX_URG);
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} else {
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ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
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if (ret)
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return ret;
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}
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/* write doorbell */
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MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
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while (1) {
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ret = ~0;
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/* Wait for doorbell from SDM */
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while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
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;
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if (!ret)
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return -ETIMEDOUT;
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/* clear interrupt */
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MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
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if (urgent) {
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u32 new_status = MBOX_READL(MBOX_STATUS);
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/* Urgent ACK is toggled */
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if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
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return 0;
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return -ECOMM;
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}
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/* read current response offset */
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rout = MBOX_READL(MBOX_ROUT);
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/* read response valid offset */
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rin = MBOX_READL(MBOX_RIN);
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if (rout != rin) {
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/* Response received */
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resp = MBOX_READ_RESP_BUF(rout);
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rout++;
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/* wrapping around when it reach the buffer size */
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rout %= MBOX_RESP_BUFFER_SIZE;
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/* update next ROUT */
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MBOX_WRITEL(rout, MBOX_ROUT);
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/* check client ID and ID */
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if ((MBOX_RESP_CLIENT_GET(resp) ==
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MBOX_CLIENT_ID_UBOOT) &&
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(MBOX_RESP_ID_GET(resp) == id)) {
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ret = MBOX_RESP_ERR_GET(resp);
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if (ret)
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return ret;
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if (resp_buf_len) {
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buf_len = *resp_buf_len;
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*resp_buf_len = 0;
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} else {
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buf_len = 0;
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}
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resp_len = MBOX_RESP_LEN_GET(resp);
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while (resp_len) {
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ret = mbox_polling_resp(rout);
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if (ret)
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return ret;
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/* we need to process response buffer
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* even caller doesn't need it
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*/
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resp = MBOX_READ_RESP_BUF(rout);
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rout++;
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resp_len--;
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rout %= MBOX_RESP_BUFFER_SIZE;
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MBOX_WRITEL(rout, MBOX_ROUT);
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if (buf_len) {
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/* copy response to buffer */
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resp_buf[*resp_buf_len] = resp;
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(*resp_buf_len)++;
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buf_len--;
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}
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}
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return ret;
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}
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}
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};
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return -EIO;
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}
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int mbox_init(void)
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{
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int ret;
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/* enable mailbox interrupts */
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MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
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/* Ensure urgent request is cleared */
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MBOX_WRITEL(0, MBOX_URG);
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/* Ensure the Doorbell Interrupt is cleared */
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MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
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NULL, 1, 0, NULL);
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if (ret)
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return ret;
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/* Renable mailbox interrupts after MBOX_RESTART */
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MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
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return 0;
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}
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#ifdef CONFIG_CADENCE_QSPI
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int mbox_qspi_close(void)
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{
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return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
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0, NULL, 0, 0, NULL);
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}
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int mbox_qspi_open(void)
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{
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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int ret;
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u32 resp_buf[1];
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u32 resp_buf_len;
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
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0, NULL, 0, 0, NULL);
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if (ret) {
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/* retry again by closing and reopen the QSPI again */
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ret = mbox_qspi_close();
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if (ret)
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return ret;
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
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MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
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if (ret)
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return ret;
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}
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/* HPS will directly control the QSPI controller, no longer mailbox */
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resp_buf_len = 1;
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
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0, NULL, 0, (u32 *)&resp_buf_len,
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(u32 *)&resp_buf);
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if (ret)
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goto error;
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/* We are getting QSPI ref clock and set into sysmgr boot register */
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printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
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writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
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return 0;
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error:
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mbox_qspi_close();
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return ret;
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}
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#endif /* CONFIG_CADENCE_QSPI */
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int mbox_reset_cold(void)
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{
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int ret;
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
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0, NULL, 0, 0, NULL);
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if (ret) {
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/* mailbox sent failure, wait for watchdog to kick in */
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hang();
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}
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return 0;
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}
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/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
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static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
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{
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u32 reconfig_status_resp_len;
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u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
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int ret;
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reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
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ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
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MBOX_CMD_DIRECT, 0, NULL, 0,
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&reconfig_status_resp_len,
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reconfig_status_resp);
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if (ret)
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return ret;
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/* Check for any error */
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ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
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if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
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return ret;
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/* Make sure nStatus is not 0 */
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ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
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if (!(ret & RCF_PIN_STATUS_NSTATUS))
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return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
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ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
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if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
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return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
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if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
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(ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
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!reconfig_status_resp[RECONFIG_STATUS_STATE])
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return 0; /* configuration success */
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return MBOX_CFGSTAT_STATE_CONFIG;
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}
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int mbox_get_fpga_config_status(u32 cmd)
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{
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return mbox_get_fpga_config_status_common(cmd);
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}
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int __secure mbox_get_fpga_config_status_psci(u32 cmd)
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{
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return mbox_get_fpga_config_status_common(cmd);
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}
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int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
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u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
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{
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return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
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resp_buf_len, resp_buf);
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}
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int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
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u32 *arg, u8 urgent, u32 *resp_buf_len,
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u32 *resp_buf)
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{
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return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
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resp_buf_len, resp_buf);
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}
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int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
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{
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return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
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}
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int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
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u32 *arg)
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{
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return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
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}
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int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
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{
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return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
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}
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int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
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{
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return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
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}
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